def INC(cpu: CPU6502): value = cpu.fetch() value += 1 cpu.cpu_write(cpu.state.addr_abs, value & 0xff) cpu.state.set_flag(Flags6502.Z, (value & 0xff) == 0x00) cpu.state.set_flag(Flags6502.N, value & 0x0080) return 0
def RTI(cpu: CPU6502): cpu.state.status = cpu.pop_value_from_stack() cpu.state.set_flag(Flags6502.U, 1) cpu.state.set_flag(Flags6502.B, 0) cpu.pop_program_counter_from_stack() return 0
def RLA(cpu: CPU6502): fetched = cpu.fetch() & 0XFF fetched = (fetched << 1) | cpu.state.get_flag(Flags6502.C) cpu.state.set_flag(Flags6502.C, fetched & 0xFF00) cpu.state.a = cpu.state.a & fetched cpu.state.set_flag(Flags6502.Z, cpu.state.a == 0x00) cpu.state.set_flag(Flags6502.N, cpu.state.a & 0x80) cpu.cpu_write(cpu.state.addr_abs, fetched & 0xFF) return 0
def IZX(cpu: CPU6502): t = cpu.cpu_read(cpu.state.pc) cpu.state.pc += 1 lo = cpu.cpu_read((t + cpu.state.x) & 0x00ff) hi = cpu.cpu_read((t + cpu.state.x + 1) & 0x00ff) cpu.state.addr_abs = (hi << 8) | lo return 0
def RRA(cpu: CPU6502): m = cpu.fetch() carry = m & 0x01 m = (cpu.state.get_flag(Flags6502.C) << 7) | (m >> 1) m &= 0xFF cpu.state.set_flag(Flags6502.C, carry) _add(cpu, m) cpu.cpu_write(cpu.state.addr_abs, m & 0xFF) return 0
def SLO(cpu: CPU6502): m = cpu.fetch() & 0xFF m <<= 1 cpu.state.a |= (m & 0xff) cpu.state.set_flag(Flags6502.C, m & 0xFF00) cpu.state.set_flag(Flags6502.Z, cpu.state.a == 0x00) cpu.state.set_flag(Flags6502.N, cpu.state.a & 0x80) cpu.cpu_write(cpu.state.addr_abs, m & 0xFF) return 0
def SRE(cpu: CPU6502): m = cpu.fetch() & 0xFF cpu.state.set_flag(Flags6502.C, m & 0x01) m = (m >> 1) & 0xFF cpu.state.a ^= m cpu.state.set_flag(Flags6502.Z, cpu.state.a == 0x00) cpu.state.set_flag(Flags6502.N, cpu.state.a & 0x80) cpu.cpu_write(cpu.state.addr_abs, m & 0xFF) return 0
def LSR(cpu: CPU6502): fetched = cpu.fetch() & 0xFF cpu.state.set_flag(Flags6502.C, fetched & 0x01) fetched = (fetched >> 1) & 0xFF cpu.state.set_flag(Flags6502.Z, fetched == 0x00) cpu.state.set_flag(Flags6502.N, 0) if lookup[cpu.state.opcode].addr_mode == IMP: cpu.state.a = fetched else: cpu.cpu_write(cpu.state.addr_abs, fetched) return 0
def ROL(cpu: CPU6502): fetched = cpu.fetch() & 0XFF fetched = (fetched << 1) | cpu.state.get_flag(Flags6502.C) cpu.state.set_flag(Flags6502.C, fetched & 0xFF00) fetched &= 0xFF cpu.state.set_flag(Flags6502.Z, fetched == 0x00) cpu.state.set_flag(Flags6502.N, fetched & 0x80) if lookup[cpu.state.opcode].addr_mode == IMP: cpu.state.a = fetched else: cpu.cpu_write(cpu.state.addr_abs, fetched) return 0
def IND(cpu: CPU6502): ptr_lo, ptr_hi = cpu.cpu_read_2(cpu.state.pc) cpu.state.pc += 2 ptr = (ptr_hi << 8) | ptr_lo if ptr_lo == 0x00ff: # Simulate page boundary hardware bug cpu.state.addr_abs = ( cpu.cpu_read(ptr & 0xff00) << 8) | cpu.cpu_read(ptr + 0) else: cpu.state.addr_abs = (cpu.cpu_read(ptr + 1) << 8) | cpu.cpu_read(ptr + 0) return 0
def IZY(cpu: CPU6502): t = cpu.cpu_read(cpu.state.pc) cpu.state.pc += 1 lo = cpu.cpu_read(t & 0x00ff) hi = cpu.cpu_read((t + 1) & 0x00ff) addr = ((hi << 8) | lo) + cpu.state.y cpu.state.addr_abs = addr & 0xFFFF if (addr & 0xff00) != (hi << 8): return 1 else: return 0
def ROR(cpu: CPU6502): fetched = cpu.fetch() carry = fetched & 0x01 fetched = (cpu.state.get_flag(Flags6502.C) << 7) | (fetched >> 1) fetched &= 0xFF cpu.state.set_flag(Flags6502.C, carry) cpu.state.set_flag(Flags6502.Z, fetched == 0x00) cpu.state.set_flag(Flags6502.N, fetched & 0x80) if lookup[cpu.state.opcode].addr_mode == IMP: cpu.state.a = fetched else: cpu.cpu_write(cpu.state.addr_abs, fetched) return 0
def LAX(cpu: CPU6502): value = cpu.fetch() & 0xFF cpu.state.a = value cpu.state.x = value cpu.state.set_flag(Flags6502.Z, value == 0x00) cpu.state.set_flag(Flags6502.N, value & 0x80) return 1
def REL(cpu: CPU6502): cpu.state.addr_rel = cpu.cpu_read(cpu.state.pc) cpu.state.pc += 1 if cpu.state.addr_rel & 0x80: cpu.state.addr_rel |= 0xff00 return 0
def CPY(cpu: CPU6502): fetched = cpu.fetch() temp = cpu.state.y - fetched cpu.state.set_flag(Flags6502.C, cpu.state.y >= fetched) cpu.state.set_flag(Flags6502.Z, (temp & 0x00ff) == 0x00) cpu.state.set_flag(Flags6502.N, temp & 0x80) return 1
def BIT(cpu: CPU6502): fetched = cpu.fetch() temp = cpu.state.a & fetched cpu.state.set_flag(Flags6502.Z, (temp & 0x00FF) == 0x00) cpu.state.set_flag(Flags6502.N, fetched & (1 << 7)) cpu.state.set_flag(Flags6502.V, fetched & (1 << 6)) return 0
def CMP(cpu: CPU6502): fetched = cpu.fetch() temp = cpu.state.a - fetched cpu.state.set_flag(Flags6502.C, (cpu.state.a & 0xFF) >= fetched) cpu.state.set_flag(Flags6502.Z, (temp & 0x00ff) == 0x00) cpu.state.set_flag(Flags6502.N, temp & 0x80) return 1
def ABY(cpu: CPU6502): lo, hi = cpu.cpu_read_2(cpu.state.pc) cpu.state.pc += 2 addr = ((hi << 8) | lo) + cpu.state.y cpu.state.addr_abs = addr & 0xFFFF if (addr & 0xff00) != (hi << 8): return 1 else: return 0
def ABX(cpu: CPU6502): lo, hi = cpu.cpu_read_2(cpu.state.pc) cpu.state.pc += 2 cpu.state.addr_abs = (hi << 8) | lo cpu.state.addr_abs += cpu.state.x if (cpu.state.addr_abs & 0xff00) != (hi << 8): return 1 else: return 0
def __init__(self): self.cpu = CPU6502(self) self.ppu = PPU2C02(self) self.cart: Cartridge = None self.cpu_ram = [0x00] * 2048 self.system_clock_counter = 0 self.controller_state = [0x00, 0x00] self.controller = [0x00, 0x00] self._dma_page = 0x00 self._dma_addr = 0x00 self._dma_data = 0x00 self._dma_transfer = False self._dma_dummy = True
def ABS(cpu: CPU6502): lo, hi = cpu.cpu_read_2(cpu.state.pc) cpu.state.pc += 2 cpu.state.addr_abs = (hi << 8) | lo return 0
def STY(cpu: CPU6502): cpu.cpu_write(cpu.state.addr_abs, cpu.state.y) return 0
def ORA(cpu: CPU6502): m = cpu.fetch() cpu.state.a |= (m & 0xff) cpu.state.set_flag(Flags6502.Z, cpu.state.a == 0x00) cpu.state.set_flag(Flags6502.N, cpu.state.a & 0x80) return 1
def PHA(cpu: CPU6502): cpu.push_value_on_stack(cpu.state.a) return 0
def SBC(cpu: CPU6502): value = cpu.fetch() value = (value & 0xffff) ^ 0x00ff _add(cpu, value) return 1
def SAX(cpu: CPU6502): temp = (cpu.state.a & cpu.state.x) cpu.cpu_write(cpu.state.addr_abs, temp) return 0
def RTS(cpu: CPU6502): cpu.pop_program_counter_from_stack() cpu.state.pc += 1 return 0
def PHP(cpu: CPU6502): cpu.push_value_on_stack(cpu.state.status | Flags6502.B | Flags6502.U) return 0
def PLA(cpu: CPU6502): cpu.state.a = cpu.pop_value_from_stack() cpu.state.set_flag(Flags6502.Z, cpu.state.a == 0x00) cpu.state.set_flag(Flags6502.N, cpu.state.a & 0x80) return 0
def PLP(cpu: CPU6502): cpu.state.status = cpu.pop_value_from_stack() cpu.state.set_flag(Flags6502.U, 1) cpu.state.set_flag(Flags6502.B, 0) return 0