def run_cim():
if len(sys.argv) <= 1:
print("usage: %s CIM_FILES" % sys.argv[0])
sys.exit(-1)
files = sys.argv[1:]
name = "python"
system = dpsim.load_cim(name, files, frequency=60)
sw = dpsim.dp.ph1.Switch("DP_SynGen_TrStab_Step_StepLoad")
sw.resistance_open = 1e9
sw.resistance_closed = 0.1
sw.closed = False
sw.connect([dpsim.dp.Node.GND(), system.nodes["BUS9"]])
system.add_component(sw)
sim = dpsim.Simulation(name,
system,
timestep=0.0001,
duration=0.1,
pbar=True)
sim.add_switch_event(sw, 0.05, True)
sim.run()
def do_sim(self, scheduler=None, scheduler_args={}, size=1):
times = []
if size > 1:
# TODO a bit ugly
copy_args = self.copy_settings.copy()
decouple = copy_args['decouple']
del (copy_args['decouple'])
for i in range(0, self.repetitions):
sys = dpsim.load_cim(self.name,
self.files,
self.frequency,
log_level=0)
if size > 1:
if decouple == 'diakoptics':
self.sim_args['tear_components'] = multiply_diakoptics(
sys, size - 1, **copy_args)
elif decouple:
multiply_decoupled(sys, size - 1, **copy_args)
else:
multiply_coupled(sys, size - 1, **copy_args)
sim = dpsim.Simulation(self.name, sys, **self.sim_args)
if scheduler:
sim.set_scheduler(scheduler, **scheduler_args)
sim.run()
times.append(sim.avg_step_time)
if 'tear_components' in self.sim_args:
del (self.sim_args['tear_components'])
avg = sum(times) / len(times)
sigma = math.sqrt(sum([(x - avg)**2 for x in times]) / len(times))
return (avg, sigma)
def test_simulation():
logging.getLogger().setLevel(logging.DEBUG)
logging.info('hello\n')
n1 = dpsim.dp.Node('n1')
gnd = dpsim.dp.Node.GND()
r = dpsim.dp.ph1.Resistor('r1', [gnd, n1])
sys = dpsim.SystemTopology(50, [n1], [r])
sim = dpsim.Simulation(__name__,
sys,
duration=10,
rt=True,
pbar=True,
single_stepping=True)
sim.step()
assert sim.wait_until() == Event.starting
assert sim.wait_until() == Event.running
assert sim.wait_until() == Event.paused
for x in range(2, 10):
sim.step()
assert sim.wait_until() == Event.resuming
assert sim.wait_until() == Event.running
assert sim.wait_until() == Event.paused
assert sim.steps == x
sim.stop()
assert sim.wait_until() == Event.stopping
assert sim.wait_until() == Event.stopped
def do_sim(name, system):
logger = dpsim.Logger(name)
logger.log_attribute(system.nodes['BUS5'], 'v')
logger.log_attribute(system.nodes['BUS6'], 'v')
logger.log_attribute(system.nodes['BUS8'], 'v')
sim = dpsim.Simulation(name, system, timestep=0.0001, duration=0.1, init_steady_state=False, pbar=False, split_subnets=True)
sim.add_logger(logger)
sim.run()
def do_sim(name, system):
logger = dpsim.Logger(name)
for i in range(0, 6):
logger.log_attribute(system.nodes['BUS' + str(i + 4)], 'v')
sim = dpsim.Simulation(name,
system,
timestep=0.0001,
duration=0.1,
init_steady_state=False,
pbar=False,
split_subnets=True)
sim.set_scheduler('thread_level', threads=4)
sim.add_logger(logger)
sim.run()
def test_simulation():
logging.getLogger().setLevel(logging.DEBUG)
logging.info('hello\n')
n1 = dpsim.dp.Node('n1')
gnd = dpsim.dp.Node.GND()
r = dpsim.dp.ph1.Resistor('r1', [gnd, n1])
sys = dpsim.SystemTopology(50, [n1], [r])
sim = dpsim.Simulation(__name__, sys, duration=10, pbar=True)
sim.start()
assert sim.wait_until() == Event.starting
assert sim.wait_until() == Event.running
sim.pause()
assert sim.wait_until() == Event.pausing
assert sim.wait_until() == Event.paused
steps_start = sim.steps
while sim.steps < steps_start + 100:
steps_before = sim.steps
sim.step()
assert sim.wait_until() == Event.resuming
assert sim.wait_until() == Event.running
assert sim.wait_until() == Event.paused
assert steps_before + 1 == sim.steps
sim.start()
assert sim.wait_until() == Event.resuming
assert sim.wait_until() == Event.running
sim.stop()
assert sim.wait_until() == Event.stopping
assert sim.wait_until() == Event.stopped
def run(self):
# Nodes
gnd = dpsim.dp.Node.GND()
n3 = dpsim.dp.Node('n3')
# Components
ecs = dpsim.dp.ph1.CurrentSource('i_ext', [n3, gnd], 0 + 0j)
r1 = dpsim.dp.ph1.Resistor('r_1', [n3, gnd], 1)
intf = dpsim.open_interface('/dpsim21', '/dpsim12', samplelen=2)
intf.import_attribute(ecs, 'I_ref', 1, 0, 1)
intf.export_attribute(r1, 'v_comp', 1, 0, 1)
sys = dpsim.SystemTopology(50, [gnd, n3], [ecs, r1])
sim = dpsim.Simulation('shmem2', sys, duration=1)
sim.add_interface(intf)
print('Starting simulation on right side')
sim.run()
def run(self):
# Nodes
gnd = dpsim.dp.Node.GND()
n1 = dpsim.dp.Node('n1')
n2 = dpsim.dp.Node('n2')
vs = dpsim.dp.ph1.VoltageSourceNorton('v_s', [n1, gnd], 10000 + 0j, 1)
evs = dpsim.dp.ph1.VoltageSource('v_ext', [n2, gnd], 0 + 0j)
l1 = dpsim.dp.ph1.Inductor('l_1', [n1, n2], 1e-3)
intf = dpsim.open_interface('/dpsim12', '/dpsim21', samplelen=2)
intf.import_attribute(evs, 'V_ref', 1, 0, 1)
intf.export_attribute(evs, 'i_comp', 1, 0, 1)
sys = dpsim.SystemTopology(50, [gnd, n1, n2], [evs, vs, l1])
sim = dpsim.Simulation('shmem1', sys, duration=1)
sim.add_interface(intf)
print('Starting simulation on left side')
sim.run()
def test_circuit():
# Nodes
gnd = dpsim.dp.Node.GND()
n1 = dpsim.dp.Node('n1')
n2 = dpsim.dp.Node('n2')
n3 = dpsim.dp.Node('n3')
# Components
v1 = dpsim.dp.ph1.VoltageSource('v_1')
v1.V_ref= complex(10, 0)
lL = dpsim.dp.ph1.Inductor('l_L')
lL.L= 0.001
rL = dpsim.dp.ph1.Resistor('r_L')
rL.R= 0.1
r1 = dpsim.dp.ph1.Resistor('r_1')
r1.R= 20
v1.connect([gnd, n1])
lL.connect([n2, n3])
rL.connect([n1, n2])
r1.connect([n3, gnd])
system = dpsim.SystemTopology(50, [gnd, n1, n2, n3], [v1, lL, rL, r1])
sim = dpsim.Simulation(__name__, system, duration=0.2, timestep=0.0005)
sim.run()
#results = rt.read_timeseries_dpsim_cmpl('Logs/' + sim.name + '_LeftVector.csv')
#expected = rt.read_timeseries_dpsim_real('Examples/Results/Simulink/Circuits/SL_' + sim.name() + '.csv')
err = 0
#err += ts.TimeSeries.rmse(expected[0], results[0].dynphasor_shift_to_emt('n1_emt', 50))
#err += ts.TimeSeries.rmse(expected[1], results[1].dynphasor_shift_to_emt('n2_emt', 50))
print('Total RMSE: %g' % (err))
assert err < 1e-4
threads = [1, 2, 4, 8, 16]
sizes = range(1, 32)
scheduler = 'thread_level'
reps = 5
for size in sizes:
filename = "measurements_" + str(size) + ".txt"
if not os.path.isfile(filename):
system = dpsim.load_cim(name, files, frequency=60)
if size > 1:
system.multiply(size - 1)
sim = dpsim.Simulation(name,
system,
timestep=0.001,
duration=0.5,
init_steady_state=True,
pbar=False,
split_subnets=True,
log_level=0)
sim.set_scheduler('sequential', out_measurement_file=filename)
sim.run()
step_times = {}
for n in threads:
step_times[n] = []
for size in sizes:
rep_times = []
for i in range(0, reps):
system = dpsim.load_cim(name, files, frequency=60)
if size > 1:
system.multiply(size - 1)
