maxScalar = Hyper() numRegisters = Hyper() programLen = Hyper() numTimesteps = Hyper() inputNum = Hyper() inputStackSize = Hyper() numRegInstrs = 13 numBranchInstrs = 2 numInstrTypes = 3 numInstructions = numBranchInstrs + numRegInstrs + 1 mutableStackSize = maxScalar - inputStackSize - 1 # Inputs inputRegVal = Input(maxScalar)[inputNum] inputStackCarVal = Input(maxScalar)[inputStackSize] inputStackCdrVal = Input(maxScalar)[inputStackSize] # Outputs outputTermState = Output(2) outputRegVal = Output(maxScalar) outputListVal = Output(maxScalar)[maxScalar] # Runtime state stackCarValue = Var(maxScalar)[numTimesteps + 1, mutableStackSize] stackCdrValue = Var(maxScalar)[numTimesteps + 1, mutableStackSize] stackPtr = Var(mutableStackSize)[numTimesteps + 1] registers = Var(maxScalar)[numTimesteps + 1, numRegisters]
# - 1 for Nil # - inputStackSize # - prefixLength (as each instruction can allocate) # - maxLoopsteps (as we create a list element for each map/zipWith iteration) # - maxLoopsteps * lambdaLength (as each lambda instruction can allocate) # - suffixLength (as each instruction can allocate) stackPtrAtPrefixStart = 1 + inputStackSize stackPtrAtCombinatorStart = stackPtrAtPrefixStart + prefixLength if lambdaLength > 0: stackPtrAtSuffixStart = stackPtrAtCombinatorStart + maxLoopsteps * ( 1 + lambdaLength) else: stackPtrAtSuffixStart = stackPtrAtCombinatorStart stackSize = stackPtrAtSuffixStart + suffixLength inputRegIntVal = Input(maxInt)[inputNum] inputRegPtrVal = Input(stackSize)[inputNum] inputRegBoolVal = Input(2)[inputNum] inputStackCarVal = Input(maxInt)[inputStackSize] inputStackCdrVal = Input(stackSize)[inputStackSize] #### Outputs: expectListOutput = Input(2) outputRegIntVal = Output(maxInt) outputRegBoolVal = Output(2) outputListVal = Output(maxInt)[stackSize] outputListIsDone = Output(2)[stackSize] outputTermState = Output(2) #### Execution model description ## Combinators: foldl, map, zipWith
from dummy import Hyper, Param, Var, Runtime, Input, Output, Inline numBlocks = Hyper() numRegisters = Hyper() numTimesteps = Hyper() maxInt = Hyper() # Inputs and Outputs boolSize = 2 initial_memory = Input(maxInt)[maxInt] final_is_halted = Output(boolSize) final_memory = Output(maxInt)[maxInt] # Interpreter instruction details / implementations numInstructions = 16 @Runtime([], maxInt) def Zero(): return 0 @Runtime([maxInt], maxInt) def Inc(a): return (a + 1) % maxInt @Runtime([maxInt, maxInt], maxInt) def Add(a, b): return (a + b) % maxInt
stackPtrAtCombinatorStart = stackPtrAtPrefixStart + prefixLength if lambdaLength > 0: stackPtrAtSuffixStart = stackPtrAtCombinatorStart + maxLoopsteps * ( 1 + lambdaLength) numTimesteps = prefixLength + ( (lambdaLength + 1) * maxLoopsteps) + suffixLength + 2 else: stackPtrAtSuffixStart = stackPtrAtCombinatorStart numTimesteps = prefixLength + suffixLength + 2 stackSize = stackPtrAtSuffixStart + suffixLength maxScalar = stackSize + 0 registerNum = inputNum + extraRegisterNum lambdaRegisterNum = registerNum + 3 inputRegVal = Input(maxScalar)[inputNum] inputStackCarVal = Input(maxScalar)[inputStackSize] inputStackCdrVal = Input(stackSize)[inputStackSize] #### Outputs: expectListOutput = Input(2) outputRegVal = Output(maxScalar) outputListVal = Output(maxScalar)[stackSize] outputListIsDone = Output(2)[stackSize] outputTermState = Output(2) #### Execution model description ## Combinators: foldl, map, zipWith numCombinators = 3 ## Instructions: cons, cdr, car, nil/zero/false, add, inc, eq, gt, and, ite,
# The number of stack cells is dependent on the number of instructions and inputs as follows: # - 1 for Nil # - inputStackSize # - prefixLength (as each instruction can allocate a cell) # - maxLoopsteps (as we create one cell after each iteration) # - maxLoopsteps * loopBodyLength (as each loopBody instruction can allocate a cell) # - suffixLength (as each instruction can allocate a cell) stackPtrAtPrefixStart = 1 + inputStackSize stackPtrAtLoopStart = stackPtrAtPrefixStart + prefixLength stackSize = stackPtrAtLoopStart + maxLoopsteps * loopBodyLength + suffixLength # Registers allow the inputs, the extras, and three additional ones in the loop: registerNum = inputNum + extraRegisterNum loopRegisterNum = registerNum + 2 inputRegIntVal = Input(maxInt)[inputNum] inputRegPtrVal = Input(stackSize)[inputNum] inputRegBoolVal = Input(2)[inputNum] inputStackIntVal = Input(maxInt)[inputStackSize] inputStackPtrVal = Input(stackSize)[inputStackSize] #### Outputs outputRegIntVal = Output(maxInt) outputRegPtrVal = Var( stackSize) #Data structure output is special, see end of file outputRegBoolVal = Output(2) outputListVal = Output(maxInt)[stackSize] #### Execution model description ## Loops: foreach in l, foreach in zip l1, l2 numLoops = 2
from dummy import Hyper, Param, Var, Runtime, Input, Output, Inline numTapeSymbols = Hyper() numHeadStates = Hyper() tapeLength = Hyper() numTimesteps = Hyper() boolSize = 2 numDirections = 3 # Inputs and Output initial_tape = Input(numTapeSymbols)[tapeLength] final_is_halted = Output(2) final_tape = Output(numTapeSymbols)[tapeLength] # Turing Machine parameters write = Param(numTapeSymbols)[numHeadStates, numTapeSymbols] dir = Param(numDirections)[numHeadStates, numTapeSymbols] newState = Param(numHeadStates)[numHeadStates, numTapeSymbols] @Runtime([tapeLength, numDirections], tapeLength) def move(pos, dir): if dir == 0: return pos elif dir == 1: return (pos + 1) % tapeLength elif dir == 2: return (pos - 1) % tapeLength @Runtime([tapeLength, tapeLength], boolSize)
@Runtime([2], 2) def NOP(a): return a @Runtime([numWires, numWires], 2) def equalityTest(a, b): return 1 if a == b else 0 gate = Param(numGateTypes)[numGates] in1 = Param(numWires)[numGates] in2 = Param(numWires)[numGates] out = Param(numWires)[numGates] initial_wires = Input(2)[numWires] final_wires = Output(2)[numOutputs] wires = Var(2)[numGates + 1, numWires] tmpOutput = Var(2)[numGates] tmpDoWrite = Var(2)[numGates, numWires] tmpArg1 = Var(2)[numGates] tmpArg2 = Var(2)[numGates] for w in range(numWires): wires[0, w].set_to(initial_wires[w]) for g in range(numGates): with in1[g] as i1: tmpArg1[g].set_to(wires[g, i1])