("r8l", REG_R8, 0, 8),
("r9l", REG_R9, 0, 8),
("r10l", REG_R10, 0, 8),
("r11l", REG_R11, 0, 8),
("r12l", REG_R12, 0, 8),
("r13l", REG_R13, 0, 8),
("r14l", REG_R14, 0, 8),
("r15l", REG_R15, 0, 8),
# Flags
("TF", REG_EFLAGS, 8, 1),
]
# Add the meta's indexes
e_reg.addLocalMetas(l, amd64meta)
# DIS NOTES:
# the REX prefix must be the *last* non escape (0f) prefix
# EMU NOTES:
# In 64 bit mode, all 32 bit dest regs get 0 extended into the rest of the bits
# In 64 bit mode, all 8/16 bit accesses do NOT modify the upper bits
# In 64 bit mode, all near branches, and implicit RSP (push pop) use RIP even w/o REX
# In 64 bit mode, if mod/rm is mod=0 and r/m is 5, it's RIP relative IMM32
import envi.archs.i386.opcode86 as opcode86
class Amd64RipRelOper(envi.Operand):
def __init__(self, imm, tsize):
self.imm = imm
self.tsize = tsize
("dl", REG_EDX, 0, 8),
("bl", REG_EBX, 0, 8),
("ah", REG_EAX, 8, 8),
("ch", REG_ECX, 8, 8),
("dh", REG_EDX, 8, 8),
("bh", REG_EBX, 8, 8),
]
statmetas = [
('CF', REG_EFLAGS, 0, 1, 'Carrie Flag'),
('PF', REG_EFLAGS, 2, 1, 'Parity Flag'),
('AF', REG_EFLAGS, 4, 1, 'Adjust Flag'),
('ZF', REG_EFLAGS, 6, 1, 'Zero Flag'),
('SF', REG_EFLAGS, 7, 1, 'Sign Flag'),
('TF', REG_EFLAGS, 8, 1, 'Trap Flag'),
('IF', REG_EFLAGS, 9, 1, 'Interrupt Enable Flag'),
('DF', REG_EFLAGS, 10, 1, 'Direction Flag'),
('OF', REG_EFLAGS, 11, 1, 'Overflow Flag'),
]
e_reg.addLocalStatusMetas(l, i386meta, statmetas, 'EFLAGS')
e_reg.addLocalMetas(l, i386meta)
class i386RegisterContext(e_reg.RegisterContext):
def __init__(self):
e_reg.RegisterContext.__init__(self)
self.loadRegDef(i386regs)
self.loadRegMetas(i386meta, statmetas=statmetas)
self.setRegisterIndexes(REG_EIP, REG_ESP, srindex=REG_EFLAGS)
("IT3",REG_FLAGS, PSR_IT+3, 1, "IfThen 3 bit"),
("IT4",REG_FLAGS, PSR_IT+4, 1, "IfThen 4 bit"),
("IT5",REG_FLAGS, PSR_IT+5, 1, "IfThen 5 bit"),
("IT6",REG_FLAGS, PSR_IT+6, 1, "IfThen 6 bit"),
("IT7",REG_FLAGS, PSR_IT+7, 1, "IfThen 7 bit"),
("E", REG_FLAGS, PSR_E, 1, "Data Endian bit"),
("A", REG_FLAGS, PSR_A, 1, "Imprecise Abort Disable bit"),
("I", REG_FLAGS, PSR_I, 1, "IRQ disable bit"),
("F", REG_FLAGS, PSR_F, 1, "FIQ disable bit"),
("T", REG_FLAGS, PSR_T, 1, "Thumb Mode bit"),
("M", REG_FLAGS, PSR_M, 5, "Processor Mode"),
]
arm_metas = [
("R13", REG_SP, 0, 32),
("R14", REG_LR, 0, 32),
("R15", REG_PC, 0, 32),
]
e_reg.addLocalStatusMetas(l, arm_metas, arm_status_metas, "CPSC")
e_reg.addLocalMetas(l, arm_metas)
class ArmRegisterContext(e_reg.RegisterContext):
def __init__(self):
e_reg.RegisterContext.__init__(self)
self.loadRegDef(reg_data)
self.loadRegMetas(arm_metas, statmetas=arm_status_metas)
self.setRegisterIndexes(REG_PC, REG_SP)
i386meta = [
("ax", REG_EAX, 0, 16),
("cx", REG_ECX, 0, 16),
("dx", REG_EDX, 0, 16),
("bx", REG_EBX, 0, 16),
("sp", REG_ESP, 0, 16),
("bp", REG_EBP, 0, 16),
("si", REG_ESI, 0, 16),
("di", REG_EDI, 0, 16),
("al", REG_EAX, 0, 8),
("cl", REG_ECX, 0, 8),
("dl", REG_EDX, 0, 8),
("bl", REG_EBX, 0, 8),
("ah", REG_EAX, 8, 8),
("ch", REG_ECX, 8, 8),
("dh", REG_EDX, 8, 8),
("bh", REG_EBX, 8, 8),
# FIXME more flags... (here and amd64)
("TF", REG_EFLAGS, 8, 1),
]
e_reg.addLocalMetas(l, i386meta)
class i386RegisterContext(e_reg.RegisterContext):
def __init__(self):
e_reg.RegisterContext.__init__(self)
self.loadRegDef(i386regs)
self.loadRegMetas(i386meta)
self.setRegisterIndexes(REG_EIP, REG_ESP)
("r15w", REG_R15, 0, 16),
("r8l", REG_R8, 0, 8),
("r9l", REG_R9, 0, 8),
("r10l", REG_R10, 0, 8),
("r11l", REG_R11, 0, 8),
("r12l", REG_R12, 0, 8),
("r13l", REG_R13, 0, 8),
("r14l", REG_R14, 0, 8),
("r15l", REG_R15, 0, 8),
# Flags
("TF", REG_EFLAGS, 8, 1),
]
# Add the meta's indexes
e_reg.addLocalMetas(l, amd64meta)
RMETA_LOW32 = 0x00200000
class Amd64RegisterContext(e_reg.RegisterContext):
def __init__(self):
self.loadRegDef(amd64regs)
self.loadRegMetas(amd64meta)
self.setRegisterIndexes(REG_RIP, REG_RSP)
def setRegister(self, index, value):
# NOTE: A special override is needed here because setting "eax" automagicall
# zero extends into RAX...
if (index & 0xffff0000) == RMETA_LOW32:
index = index & 0xffff
('I', 8),
('R', 8),
]
l = locals()
e_reg.addLocalEnums(l, z80regs)
z80meta = [
('A', REG_AF, 8, 8),
('B', REG_BC, 8, 8),
('C', REG_BC, 0, 8),
('D', REG_DE, 8, 8),
('E', REG_DE, 0, 8),
('F', REG_AF, 0, 8),
('H', REG_HL, 8, 8),
('L', REG_HL, 0, 8),
]
e_reg.addLocalMetas(l, z80meta)
class z80RegisterContext(e_reg.RegisterContext):
def __init__(self):
e_reg.RegisterContext.__init__(self)
self.loadRegDef(z80regs)
self.loadRegMetas(z80meta)
self.setRegisterIndexes(REG_PC, REG_SP)
regctx = z80RegisterContext()
e_reg.addLocalEnums(l, registers_info)
registers_meta = [
("r0", REG_PC, 0, 16),
("r1", REG_SP, 0, 16),
("r2", REG_SR, 0, 16),
("r3", REG_CG, 0, 16),
]
status_meta = [
('C', REG_SR, 0, 1, 'Carry Flag'),
('Z', REG_SR, 1, 1, 'Zero Flag'),
('N', REG_SR, 2, 1, 'Negative (Sign) Flag'),
('GIE', REG_SR, 3, 1, 'General Interrupt Enable Flag'),
('CPUOFF', REG_SR, 4, 1, 'CPU Off Flag'),
('OSCOFF', REG_SR, 5, 1, 'Oscillator Off Flag'),
('SCG0', REG_SR, 6, 1, 'System Clock Generator 0 Off Flag'),
('SCG1', REG_SR, 7, 1, 'System Clock Generotor 1 Off Flag'),
('V', REG_SR, 8, 1, 'Overflow Flag'),
]
e_reg.addLocalStatusMetas(l, registers_meta, status_meta, 'SR')
e_reg.addLocalMetas(l, registers_meta)
class Msp430RegisterContext(e_reg.RegisterContext):
def __init__(self):
e_reg.RegisterContext.__init__(self)
self.loadRegDef(registers_info)
self.loadRegMetas([], statmetas=status_meta)
self.setRegisterIndexes(REG_PC, REG_SP, srindex=REG_SR)
("I", 8),
("R", 8),
]
l = locals()
e_reg.addLocalEnums(l, z80regs)
z80meta = [
("A", REG_AF, 8, 8),
("B", REG_BC, 8, 8),
("C", REG_BC, 0, 8),
("D", REG_DE, 8, 8),
("E", REG_DE, 0, 8),
("F", REG_AF, 0, 8),
("H", REG_HL, 8, 8),
("L", REG_HL, 0, 8),
]
e_reg.addLocalMetas(l, z80meta)
class z80RegisterContext(e_reg.RegisterContext):
def __init__(self):
e_reg.RegisterContext.__init__(self)
self.loadRegDef(z80regs)
self.loadRegMetas(z80meta)
self.setRegisterIndexes(REG_PC, REG_SP)
regctx = z80RegisterContext()
