def __init__(self, memory, start_address):
self.memory = memory
self.start_address = start_address
self.register_file = RegisterFile()
self.data_memory_key_fn = lambda: -777
self.data_memory = defaultdict(self.data_memory_key_fn)
self.cycle_count = 0
self.instr_count = 0
self.PC = 0
self.fetch_input_buffer = FetchInputBuffer({
'PC':
self.start_address,
'instr_count':
self.instr_count,
})
self.fetcher_buffer = FetcherBuffer()
self.fetch_stage = FetchStage(self.memory, self.fetch_input_buffer,
self.fetcher_buffer)
self.decoder_buffer = DecoderBuffer()
self.decode_stage = DecodeStage(self.fetcher_buffer,
self.decoder_buffer,
self.register_file)
self.executer_buffer = ExecuterBuffer()
self.execute_stage = ExecuteStage(self.decoder_buffer,
self.executer_buffer)
self.memory_buffer = MemoryBuffer()
self.memory_stage = MemoryStage(self.executer_buffer,
self.memory_buffer, self.data_memory)
self.write_back_stage = WriteBackStage(self.memory_buffer,
self.register_file)
def __init__(self, hex_code_file, initial_state_file):
"""Initialize Processor with program and memory and reg state.
Create RegisterFiles.
Create the stages - Fetch, Decode, and Execution.
"""
self.npc_line = [0]
self.Memory = defaultdict(lambda: 0)
# instruction_cache = hex_code_file.readlines()
# Get all non-empty lines
instruction_cache = [
line.strip() for line in hex_code_file if line.strip()
]
print 'instruction_cache: ', instruction_cache
self.instr_queue = []
self.FPRegisterFile = [{
'Value': i + 1,
'Busy': False,
'ROB_index': 0
} for i in xrange(10)]
self.IntRegisterFile = [{
'Value': 0,
'Busy': False,
'ROB_index': 0
} for i in xrange(32)]
self.set_initial_state(initial_state_file)
self.CDB = []
self.ROB = ROB(ROB_MAX_SIZE, self.CDB, self.IntRegisterFile,
self.Memory, self)
self.execute_module = ExecutionModule(self.Memory, self.CDB, self.ROB)
self.fetch_buffer = dict()
self.fetch_buffer['IR'] = ''
self.fetch_stage = FetchStage(0, self.npc_line, self.fetch_buffer,
instruction_cache)
self.decode_stage = DecodeStage(self.fetch_buffer)
self.issue_stage = IssueStage(self.ROB, self.instr_queue,
self.IntRegisterFile,
self.FPRegisterFile, self.execute_module)
self.write_stage = WriteStage(self.execute_module)
self.commit_stage = CommitStage(self.ROB)
self.execute_stage = ExecuteStage(self.execute_module, self.CDB,
self.ROB)
self.modules = [
self.issue_stage, self.execute_stage, self.write_stage,
self.commit_stage
]
self.num_of_instructions = 0
self.num_of_cycles = 0
def get_stage_output(memory, register_file, pc, instr_count, stage_name):
"""Return the output buffer of stage given the initial conditions.
All the stages before stage_name will be executed.
Arguments:
- `memory`:
- `register_file`:
- `pc`:
- `stage_name`:
TODO: Maybe just take the stages as input later.
"""
fetch_input_buffer = FetchInputBuffer({
'PC': pc,
'instr_count': instr_count,
})
fetcher_buffer = FetcherBuffer()
fetch_stage = FetchStage(memory, fetch_input_buffer, fetcher_buffer)
fetch_stage.fetch_instruction()
if stage_name == 'fetch':
return fetch_stage.fetcher_buffer
decode_stage = DecodeStage(fetch_stage.fetcher_buffer, DecoderBuffer(),
register_file)
decode_stage.decode_instruction()
if stage_name == 'decode':
return decode_stage.decoder_buffer
execute_stage = ExecuteStage(decode_stage.decoder_buffer,
ExecuterBuffer())
execute_stage.execute()
if stage_name == 'execute':
return execute_stage.executer_buffer
data_memory_key_fn = lambda: -1
data_memory = defaultdict(data_memory_key_fn)
memory_stage = MemoryStage(execute_stage.executer_buffer,
MemoryBuffer(), data_memory)
memory_stage.do_memory_operation()
if stage_name == 'memory':
return memory_stage.memory_buffer
