def __init__(self):
self.opcodes = {
0xF8: P(self.set_stuff, Reg32.CF, 0),
0xFC: P(self.set_stuff, Reg32.DF, 0),
0xF9: P(self.set_stuff, Reg32.CF, 1),
0xFD: P(self.set_stuff, Reg32.DF, 1)
}
def __init__(self):
self.opcodes = {
0xF8: P(self.set_stuff, 'CF', 0),
0xFC: P(self.set_stuff, 'DF', 0),
0xF9: P(self.set_stuff, 'CF', 1),
0xFD: P(self.set_stuff, 'DF', 1),
}
def __init__(self):
self.opcodes = {
0x0FA4: P(self.shift, operation=Shift.SHL, cnt=Shift.C_imm8),
0x0FA5: P(self.shift, operation=Shift.SHL, cnt=Shift.C_CL),
0x0FAC: P(self.shift, operation=Shift.SHR, cnt=Shift.C_imm8),
0x0FAD: P(self.shift, operation=Shift.SHR, cnt=Shift.C_CL)
}
def __init__(self):
self.opcodes = {
0x0FBE: P(self.r_rm, _8bit=True, movsxd=False),
0x0FBF: P(self.r_rm, _8bit=False, movsxd=False),
0x63: P(self.r_rm, _8bit=False, movsxd=True),
0x0FB6: P(self.r_rm_movzx, _8bit=True),
0x0FB7: P(self.r_rm_movzx, _8bit=False),
}
def __init__(self):
self.opcodes = {
0xF6: P(self.rm, _8bit=True),
0xF7: P(self.rm, _8bit=False),
0x0FAF: self.r_rm,
0x6B: P(self.r_rm_imm, _8bit_imm=True),
0x69: P(self.r_rm_imm, _8bit_imm=True)
}
def __init__(self):
self.opcodes = {
0xDB:
P(self.m_int, is32bit=True, REG=0),
0xDF: [
P(self.m_int, is32bit=False, REG=0),
P(self.m_int, is32bit=False, REG=5),
]
}
def __init__(self):
self.opcodes = {
0xF6:
[P(self.div, _8bit=True),
P(self.div, _8bit=True, idiv=True)],
0xF7:
[P(self.div, _8bit=False),
P(self.div, _8bit=False, idiv=True)]
}
def __init__(self):
self.opcodes = {
**{0xD8F0 + i: P(self.fdiv, i=i, reverse=True)
for i in range(8)},
**{0xDCF8 + i: P(self.fdiv, i=i, reverse=False)
for i in range(8)},
**{0xDEF8 + i: P(self.fdivp, i=i)
for i in range(8)},
}
def __init__(self):
self.opcodes = {
# FLD
0xD9: P(self.m_fp, bits=32, REG=0),
0xDD: P(self.m_fp, bits=64, REG=0),
0xDB: P(self.m_fp, bits=80, REG=5),
**{0xD9C0 + i: P(self.m_st, i=i)
for i in range(8)}
}
def __init__(self):
self.opcodes = {
**{o: self.r
for o in range(0x58, 0x60)}, 0x8F: self.rm,
0x1F: P(self.sreg, 'DS'),
0x07: P(self.sreg, 'ES'),
0x17: P(self.sreg, 'SS'),
0x0FA1: P(self.sreg, 'FS', _32bit=True),
0x0FA9: P(self.sreg, 'GS', _32bit=True)
}
def __init__(self):
self.opcodes = {
0xF6: [
P(self.div, _8bit=True, REG=6), # DIV r/m8
P(self.div, _8bit=True, REG=7) # IDIV r/m8
],
0xF7: [
P(self.div, _8bit=False, REG=6), # DIV r/m
P(self.div, _8bit=False, REG=7) # IDIV r/m
]
}
def __init__(self):
self.opcodes = {
# NEG, NOT
0xF6: [
P(self.rm, _8bit=True, operation=0),
P(self.rm, _8bit=True, operation=1)
],
0xF7: [
P(self.rm, _8bit=False, operation=0),
P(self.rm, _8bit=False, operation=1)
]
}
def __init__(self):
self.opcodes = {
0xDF: [
P(self.fist, size=2, REG=2), # FIST m16int
P(self.fist, size=2, REG=3), # FISTP m16int
P(self.fist, size=8, REG=7), # FISTP m64int
],
0xDB: [
P(self.fist, size=4, REG=2), # FIST m32int
P(self.fist, size=4, REG=3), # FISTP m32int
]
}
def __init__(self):
self.opcodes = {
# NEG, NOT
0xF6: [
P(self.rm, _8bit=True, REG=3), # NEG r/m8
P(self.rm, _8bit=True, REG=2), # NOT r/m8
],
0xF7: [
P(self.rm, _8bit=False, REG=3), # NEG r/m
P(self.rm, _8bit=False, REG=2), # NOT r/m
]
}
def __getattr__(self, item):
from functools import partial as P
"""Make an alignment for easy call. You can add more patterns as below.
>>> Layers.relu_conv2d = Layers.conv2d(activation='relu')
>>> Layers.bn_conv2d = Layers.conv2d(use_batchnorm=True)
>>> Layers.sn_leaky_conv2d = Layers.conv2d(use_sn=True, activation='lrelu')
NOTE: orders do not matter.
"""
if 'deconv2d' in item:
pass
elif 'conv2d' in item:
items = item.split('_')
kwargs = {
'kernel_initializer': 'he_normal',
'kernel_regularizer': 'l2',
'use_batchnorm': False,
'use_sn': False,
}
if 'bn' in items or 'batchnorm' in items:
kwargs.update(use_batchnorm=True)
if 'sn' in items or 'spectralnorm' in items:
kwargs.update(use_sn=True)
if 'relu' in items:
kwargs.update(activation='relu')
if 'leaky' in items or 'lrelu' in items or 'leakyrelu' in items:
kwargs.update(activation='lrelu')
if 'prelu' in items:
kwargs.update(activation='prelu')
if 'tanh' in items:
kwargs.update(activation='tanh')
return P(self.conv2d, **kwargs)
elif 'conv3d' in item:
items = item.split('_')
kwargs = {
'kernel_initializer': 'he_normal',
'kernel_regularizer': 'l2',
'use_batchnorm': False,
}
if 'bn' in items or 'batchnorm' in items:
kwargs.update(use_batchnorm=True)
if 'relu' in items:
kwargs.update(activation='relu')
if 'leaky' in items or 'lrelu' in items or 'leakyrelu' in items:
kwargs.update(activation='lrelu')
if 'prelu' in items:
kwargs.update(activation='prelu')
if 'tanh' in items:
kwargs.update(activation='tanh')
return P(self.conv3d, **kwargs)
return None
def pSGD(lr, momentum=0, dampening=0, weight_decay=0, nesterov=False):
return P(
optim.SGD,
lr=lr,
momentum=momentum,
dampening=dampening,
weight_decay=weight_decay,
nesterov=nesterov,
)
def get_conds(cls, _conds: List[str]=None, **fields: QueryParam) -> str:
conds = C(
" AND ".join,
P(chain, _conds or []),
map('='.join),
map(lambda k: (k, cls._val_holder(k))),
filter(lambda k: fields[k] is not None),
fields.keys
)()
return f" WHERE {conds}" if conds else ""
def __init__(self):
self.opcodes = {
**{o: self.r
for o in range(0x50, 0x58)}, 0xFF: self.rm,
0x6A: P(self.imm, _8bit=True),
0x68: P(self.imm, _8bit=False),
0x0E: P(self.sreg, 'CS'),
0x16: P(self.sreg, 'SS'),
0x1E: P(self.sreg, 'DS'),
0x06: P(self.sreg, 'ES'),
0x0FA0: P(self.sreg, 'FS'),
0x0FA8: P(self.sreg, 'GS')
}
def pAdam(lr=1e-3,
betas=(0.9, 0.999),
eps=1e-8,
weight_decay=0,
amsgrad=False):
return P(
optim.Adam,
lr=lr,
betas=betas,
eps=eps,
weight_decay=weight_decay,
amsgrad=amsgrad,
)
def __init__(self):
self.opcodes = {
0xD9: [
P(self.m_fp, bits=32, REG=2), # FST m32fp
P(self.m_fp, bits=32, REG=3), # FSTP m32fp
],
0xDD: [
P(self.m_fp, bits=64, REG=2), # FSTP m32fp
P(self.m_fp, bits=64, REG=3), # FSTP m64fp
],
0xDB:
P(self.m_fp, bits=80, REG=7), # FSTP m80fp
**{0xDDD0 + i: P(self.st, i=i, pop=False)
for i in range(8)},
**{0xDDD8 + i: P(self.st, i=i, pop=True)
for i in range(8)}
}
def __init__(self):
self.opcodes = {
# INC
**{o: P(self.r, _8bit=False)
for o in range(0x40, 0x48)},
0xFE: [P(self.rm, _8bit=True),
P(self.rm, _8bit=True, dec=True)],
0xFF: [P(self.rm, _8bit=False),
P(self.rm, _8bit=False, dec=True)],
# DEC
**{o: P(self.r, _8bit=False, dec=True)
for o in range(0x48, 0x50)}
}
def __init__(self):
self.opcodes = {
# F*COM*
**{
0xD0E0 + i: P(self.fucom, pop=0, i=i, set_eflags=False)
for i in range(8)
},
**{
0xDDE8 + i: P(self.fucom, pop=1, i=i, set_eflags=False)
for i in range(8)
},
0xDAE9: P(self.fucom, pop=2, i=1, set_eflags=False),
# FCOMI
**{
0xDBF0 + i: P(self.fcom, pop=0, i=i, set_eflags=True)
for i in range(8)
},
# FCOMIP
**{
0xDFF0 + i: P(self.fcom, pop=1, i=i, set_eflags=True)
for i in range(8)
},
# FUCOMI
**{
0xDBE8 + i: P(self.fucom, pop=0, i=i, set_eflags=True)
for i in range(8)
},
# FUCOMIP
**{
0xDFE8 + i: P(self.fucom, pop=1, i=i, set_eflags=True)
for i in range(8)
},
}
def __init__(self):
self.opcodes = {
# INC
**{
o: P(self.r, _8bit=False, dec=False)
for o in range(0x40, 0x48)
},
0xFE: [
P(self.rm, _8bit=True, REG=0), # INC r/m8
P(self.rm, _8bit=True, REG=1) # DEC r/m8
],
0xFF: [
P(self.rm, _8bit=False, REG=0), # INC r/m
P(self.rm, _8bit=False, REG=1) # DEC r/m
],
# DEC
**{o: P(self.r, _8bit=False, dec=True)
for o in range(0x48, 0x50)}
}
def __init__(self):
self.opcodes = {
0xEB: P(self.rel, _8bit=True, jump=_JMP),
0xE9: P(self.rel, _8bit=False, jump=_JMP),
0xFF: self.rm_m,
0xEA: P(self.ptr, _8bit=False),
0xE3: P(self.rel, _8bit=True, jump=JCXZ),
**{
opcode: P(self.rel, _8bit=True, jump=JUMPS[opcode % 0x70])
for opcode in range(0x70, 0x80)
},
**{
opcode: P(self.rel, _8bit=False, jump=JUMPS[opcode % 0x0F80])
for opcode in range(0x0F80, 0x0F90)
}
}
def __init__(self):
self.opcodes = {
0xF6: P(self.mul, _8bit=True),
0xF7: P(self.mul, _8bit=False)
}
def __init__(self):
self.opcodes = {
# ADD
0x04:
P(self.r_imm, _8bit=True),
0x05:
P(self.r_imm, _8bit=False),
0x80: [
P(self.rm_imm, _8bit_op=True, _8bit_imm=True),
P(self.rm_imm, _8bit_op=True, _8bit_imm=True, sub=True),
P(self.rm_imm,
_8bit_op=True,
_8bit_imm=True,
sub=True,
cmp=True),
P(self.rm_imm, _8bit_op=True, _8bit_imm=True, carry=True),
P(self.rm_imm,
_8bit_op=True,
_8bit_imm=True,
sub=True,
carry=True),
],
0x81: [
P(self.rm_imm, _8bit_op=False, _8bit_imm=False),
P(self.rm_imm, _8bit_op=False, _8bit_imm=False, sub=True),
P(self.rm_imm,
_8bit_op=False,
_8bit_imm=False,
sub=True,
cmp=True),
P(self.rm_imm, _8bit_op=False, _8bit_imm=False, carry=True),
P(self.rm_imm,
_8bit_op=False,
_8bit_imm=False,
sub=True,
carry=True),
],
0x83: [
P(self.rm_imm, _8bit_op=False, _8bit_imm=True),
P(self.rm_imm, _8bit_op=False, _8bit_imm=True, sub=True),
P(self.rm_imm,
_8bit_op=False,
_8bit_imm=True,
sub=True,
cmp=True),
P(self.rm_imm, _8bit_op=False, _8bit_imm=True, carry=True),
P(self.rm_imm,
_8bit_op=False,
_8bit_imm=True,
sub=True,
carry=True),
],
0x00:
P(self.rm_r, _8bit=True),
0x01:
P(self.rm_r, _8bit=False),
0x02:
P(self.r_rm, _8bit=True),
0x03:
P(self.r_rm, _8bit=False),
# SUB
0x2C:
P(self.r_imm, _8bit=True, sub=True),
0x2D:
P(self.r_imm, _8bit=False, sub=True),
0x28:
P(self.rm_r, _8bit=True, sub=True),
0x29:
P(self.rm_r, _8bit=False, sub=True),
0x2A:
P(self.r_rm, _8bit=True, sub=True),
0x2B:
P(self.r_rm, _8bit=False, sub=True),
# CMP
0x3C:
P(self.r_imm, _8bit=True, sub=True, cmp=True),
0x3D:
P(self.r_imm, _8bit=False, sub=True, cmp=True),
0x38:
P(self.rm_r, _8bit=True, sub=True, cmp=True),
0x39:
P(self.rm_r, _8bit=False, sub=True, cmp=True),
0x3A:
P(self.r_rm, _8bit=True, sub=True, cmp=True),
0x3B:
P(self.r_rm, _8bit=False, sub=True, cmp=True),
# ADC
0x14:
P(self.r_imm, _8bit=True, carry=True),
0x15:
P(self.r_imm, _8bit=False, carry=True),
0x10:
P(self.rm_r, _8bit=True, carry=True),
0x11:
P(self.rm_r, _8bit=False, carry=True),
0x12:
P(self.r_rm, _8bit=True, carry=True),
0x13:
P(self.r_rm, _8bit=False, carry=True),
# SBB
0x1C:
P(self.r_imm, _8bit=True, sub=True, carry=True),
0x1D:
P(self.r_imm, _8bit=False, sub=True, carry=True),
0x18:
P(self.rm_r, _8bit=True, sub=True, carry=True),
0x19:
P(self.rm_r, _8bit=False, sub=True, carry=True),
0x1A:
P(self.r_rm, _8bit=True, sub=True, carry=True),
0x1B:
P(self.r_rm, _8bit=False, sub=True, carry=True),
}
def pStep_lr(step_size, gamma=0.1, last_epoch=-1):
return P(lr_scheduler.StepLR,
step_size=step_size,
gamma=gamma,
last_epoch=last_epoch)
def __gather_fastx(fastx_reader, fastx_writer, fastx_files, output_file):
n = 0
with fastx_writer(output_file) as writer:
for fastx_file in fastx_files:
with fastx_reader(fastx_file) as reader:
for record in reader:
n += 1
writer.writeRecord(record)
log.info("Completed gathering {n} files (with {x} records) to {f}".format(
n=len(fastx_files), f=output_file, x=n))
gather_fasta = P(__gather_fastx, FastaReader, FastaWriter)
gather_fastq = P(__gather_fastx, FastqReader, FastqWriter)
gather_gff = merge_gffs_sorted
gather_vcf = merge_vcfs_sorted
def cat_txt_with_header(input_files, output_file):
""" Concatenate input files i_fns, to output file.
Only copy header lines from the very first input file, and skip others.
"""
with open(output_file, 'w') as writer:
for i, input_file in enumerate(input_files):
with open(input_file, 'r') as reader:
for l in reader:
if len(l.strip()) == 0:
continue
def __init__(self):
self.opcodes = {
opcode: P(self.r_rm, cond=JUMPS[opcode % 0x0F40])
for opcode in range(0x0F40, 0x0F50)
}
def __init__(self):
self.opcodes = {
opcode: P(self.rm8, cond=JUMPS[opcode % 0x0F90])
for opcode in range(0x0F90, 0x0FA0)
}