def build_CPP(self, core, sim_root, src_root):
verilator_root = utils.get_verilator_root()
if verilator_root is None:
verilator_root = utils.get_verilator_root()
args = ['-c']
args += ['-I' + src_root]
args += [
'-I' + os.path.join(src_root, core.sanitized_name, s)
for s in self.include_dirs
]
args += ['-Iobj_dir']
args += ['-I' + os.path.join(verilator_root, 'include')]
args += ['-I' + os.path.join(verilator_root, 'include', 'vltstd')]
for src_file in core.verilator.src_files:
pr_info("Compiling " + src_file.name)
l = utils.Launcher(
'g++',
args +
[os.path.join(src_root, core.sanitized_name, src_file.name)],
cwd=sim_root,
stderr=open(os.path.join(sim_root, 'g++.err.log'), 'a'))
if Config().verbose:
pr_info(" C++ compilation working dir: " + sim_root)
pr_info(
" C++ compilation command: g++ " + ' '.join(args) + ' ' +
os.path.join(src_root, core.sanitized_name, src_file.name))
l.run()
def build_C(self):
args = ['-c']
args += ['-std=c99']
args += [l for l in self.libs]
args += ['-I' + s for s in self.include_dirs]
print("Compiling " + self.src_file)
utils.Launcher('gcc', args + [self.src_file], cwd=self.sim_root).run()
def build(self):
super(Verilator, self).build()
self.archives = []
for core in self.cores:
if core.verilator:
if core.verilator.archive:
self.archives += [core.sanitized_name+'.a']
self.libs += core.verilator.libs
self.include_dirs += [os.path.join(self.src_root, core.sanitized_name, d) for d in core.verilator.include_dirs]
self.include_dirs += [os.path.dirname(os.path.join(self.work_root, self.tb_toplevel))]
self.include_dirs += [self.src_root]
pr_info("Verilating source")
self._verilate()
for core in self.cores:
if core.verilator:
self._build(core, self.work_root, self.src_root)
# Do parallel builds with <number of cpus> * 2 jobs.
make_job_count = multiprocessing.cpu_count() * 2
pr_info("Building verilator executable:")
args = ['-f', 'V' + self.top_module + '.mk', '-j', str(make_job_count), 'V' + self.top_module]
l = utils.Launcher('make', args,
cwd=os.path.join(self.work_root, 'obj_dir'),
stdout = open(os.path.join(self.work_root,
'verilator.make.log'),'w'))
if Config().verbose:
pr_info(" Verilator executable working dir: "
+ os.path.join(self.work_root, 'obj_dir'))
pr_info(" Verilator executable command: make " + ' '.join(args))
l.run()
def build_SysC(self):
#src_files
args = ['-I.']
args += ['-MMD']
args += ['-I' + s for s in self.include_dirs]
args += ['-Iobj_dir']
args += ['-I' + os.path.join(self.verilator_root, 'include')]
args += ['-I' + os.path.join(self.verilator_root, 'include', 'vltstd')]
args += ['-DVL_PRINTF=printf']
args += ['-DVM_TRACE=1']
args += ['-DVM_COVERAGE=0']
args += ['-I' + os.getenv('SYSTEMC_INCLUDE')]
args += ['-Wno-deprecated']
if os.getenv('SYSTEMC_CXX_FLAGS'):
args += [os.getenv('SYSTEMC_CXX_FLAGS')]
args += ['-c']
args += ['-g']
print("Compiling " + self.src_file)
utils.Launcher(
'g++',
args + [
'-o' + os.path.splitext(os.path.basename(self.src_file))[0] +
'.o'
] + [self.src_file],
cwd=self.sim_root).run()
def patch(self, dst_dir):
# FIXME: Use native python patch instead
patches = self.provider.patches
for f in patches:
patch_file = os.path.abspath(os.path.join(self.core_root, f))
if os.path.isfile(patch_file):
self._debug(
" applying patch file: "
+ patch_file
+ "\n"
+ " to: "
+ os.path.join(dst_dir)
)
try:
utils.Launcher(
"git",
[
"apply",
"--unsafe-paths",
"--directory",
os.path.join(dst_dir),
patch_file,
],
).run()
except OSError:
print("Error: Failed to call external command 'patch'")
return False
return True
def build(self, args):
super(Ise, self).build(args)
utils.Launcher('xtclsh', [os.path.join(self.work_root, self.system.name+'.tcl')],
cwd = self.work_root,
errormsg = "Failed to make FPGA load module").run()
super(Ise, self).done()
def build_SysC(self, core, work_root, src_root):
verilator_root = utils.get_verilator_root()
args = ['-I.']
args += ['-MMD']
args += ['-I'+src_root]
args += ['-I'+s for s in self.include_dirs]
args += ['-Iobj_dir']
args += ['-I'+os.path.join(verilator_root,'include')]
args += ['-I'+os.path.join(verilator_root,'include', 'vltstd')]
args += ['-DVL_PRINTF=printf']
args += ['-DVM_TRACE=1']
args += ['-DVM_COVERAGE=0']
if os.getenv('SYSTEMC_INCLUDE'):
args += ['-I'+os.getenv('SYSTEMC_INCLUDE')]
if os.getenv('SYSTEMC'):
args += ['-I'+os.path.join(os.getenv('SYSTEMC'),'include')]
args += ['-Wno-deprecated']
if os.getenv('SYSTEMC_CXX_FLAGS'):
args += [os.getenv('SYSTEMC_CXX_FLAGS')]
args += ['-c']
args += ['-g']
for src_file in core.verilator.src_files:
pr_info("Compiling " + src_file.name)
l = utils.Launcher('g++', args + [os.path.join(src_root, core.sanitized_name, src_file.name)],
cwd=work_root,
stderr = open(os.path.join(work_root, 'g++.err.log'),'a'))
if Config().verbose:
pr_info(" SystemC compilation working dir: " + work_root)
pr_info(" SystemC compilation command: g++ " + ' '.join(args) + ' ' + os.path.join(src_root, core.sanitized_name, src_file.name))
l.run()
def pgm(self, remaining):
tcl_file_name = os.path.join(self.work_root,
self.system.sanitized_name + "_pgm.tcl")
self._write_program_tcl_file(tcl_file_name)
utils.Launcher('vivado', ['-mode', 'batch', '-source', tcl_file_name],
cwd=self.work_root,
errormsg="Failed to program the FPGA").run()
def build(self):
super(Verilator, self).build()
self.archives = []
for core_name in self.cores:
core = self.cm.get_core(core_name)
if core.verilator:
if core.verilator.archive:
self.archives += [core_name+'.a']
self.libs += core.verilator.libs
self.include_dirs += [os.path.join(self.src_root, core_name, d) for d in core.verilator.include_dirs]
self.include_dirs += [os.path.dirname(os.path.join(self.sim_root, self.tb_toplevel))]
self.include_dirs += [self.src_root]
pr_info("Verilating source")
self._verilate()
for core_name in self.cores:
core = self.cm.get_core(core_name)
if core.verilator:
self._build(core, self.sim_root, self.src_root)
pr_info("Building verilator executable:")
args = ['-f', 'V' + self.top_module + '.mk', 'V' + self.top_module]
l = utils.Launcher('make', args,
cwd=os.path.join(self.sim_root, 'obj_dir'),
stdout = open(os.path.join(self.sim_root,
'verilator.make.log'),'w'))
if Config().verbose:
pr_info(" Verilator executable working dir: "
+ os.path.join(self.sim_root, 'obj_dir'))
pr_info(" Verilator executable command: make " + ' '.join(args))
l.run()
def pgm(self, remaining):
pgm_file_name = os.path.join(self.work_root,
self.system.sanitized_name + '.pgm')
self._write_pgm_file(pgm_file_name)
utils.Launcher('impact', ['-batch', pgm_file_name],
cwd=self.work_root,
errormsg="impact tool returned an error").run()
def build(self, args):
super(Vivado, self).build(args)
utils.Launcher('vivado', ['-mode', 'batch', '-source',
os.path.join(self.work_root, self.system.sanitized_name+'.tcl')],
cwd = self.work_root,
errormsg = "Failed to build FPGA bitstream").run()
super(Vivado, self).done()
def build(self):
super(Vivado, self).build()
utils.Launcher('vivado', ['-mode', 'batch', '-source',
self.name+'.tcl'],
cwd = self.work_root,
shell=platform.system() == 'Windows',
errormsg = "Failed to build FPGA bitstream").run()
super(Vivado, self).done()
def run(self, args):
self.env = os.environ.copy()
self.env['CORE_ROOT'] = os.path.abspath(self.system.core_root)
self.env['BUILD_ROOT'] = os.path.abspath(self.build_root)
self.env['SIM_ROOT'] = os.path.abspath(self.sim_root)
#TODO: Handle arguments parsing
pr_info("Running simulation")
utils.Launcher('./V' + self.top_module,
args,
cwd=os.path.join(self.sim_root, 'obj_dir'),
env=self.env).run()
def _verilate(self):
if self.src_type == 'systemC':
args = ['--sc']
else:
args = ['--cc']
args += ['-f', self.verilator_file]
args += ['--top-module', self.top_module]
args += ['--exe']
args += ['-LDFLAGS "']
args += ['-Wl,--start-group']
args += [os.path.join(self.work_root, s) for s in self.archives]
args += ['-Wl,--end-group']
args += [l for l in self.libs]
args += ['"']
args += ['-CFLAGS ' + '-I' + i for i in self.include_dirs]
args += [
os.path.join(self.src_root, self.system.sanitized_name,
self.tb_toplevel)
]
for key, value in self.vlogparam.items():
args += ['-G{}={}'.format(key, value)]
args += self.verilator_options
cmd = utils.find_verilator()
if cmd is None:
raise RuntimeError(
"VERILATOR_ROOT not set and there is no verilator program in your PATH"
)
cmd += ' ' + ' '.join(args)
if (self.src_type == 'systemC') and not utils.check_systemc_env():
raise RuntimeError(
"Need $SYSTEMC_LIBDIR and $SYSTEMC_INCLUDE in environment or when Verilator configured"
)
l = utils.Launcher(
cmd,
shell=True,
cwd=self.work_root,
stderr=open(os.path.join(self.work_root, 'verilator.log'), 'w'),
stdout=open(os.path.join(self.work_root, 'verilator.out.log'),
'w'))
print('')
pr_info("Starting Verilator:")
if Config().verbose:
pr_info(" Verilator working dir: " + self.work_root)
pr_info(" Verilator command: " + cmd)
print('')
l.run()
def build(self):
super(Verilator, self).build()
self._verilate()
for self.src_file in self.src_files:
if self.src_file.lower().endswith('.c'):
self.build_C()
elif self.src_file.lower().endswith('.cpp'):
self.build_SysC()
else:
raise Source(self.src_type)
utils.Launcher(
'make',
['-f', 'V' + self.top_module + '.mk', 'V' + self.top_module],
cwd=os.path.join(self.sim_root, 'obj_dir')).run()
def build_main(self):
logger.info("Building simulation model")
if not os.getenv('VERILATOR_ROOT') and not utils.which('verilator'):
raise RuntimeError(
"VERILATOR_ROOT not set and there is no verilator program in your PATH"
)
# Do parallel builds with <number of cpus> * 2 jobs.
make_job_count = multiprocessing.cpu_count() * 2
_s = os.path.join(self.work_root, 'verilator.{}.log')
l = utils.Launcher('make', ['-j', str(make_job_count)],
cwd=self.work_root,
stderr=open(_s.format('err'), 'w'),
stdout=open(_s.format('out'), 'w')).run()
def run(self, args):
if not self.fusesoc_cli_parser:
self.plusarg = []
super(Verilator, self).run(args)
if self.fusesoc_cli_parser:
_args = []
for key, value in self.plusarg.items():
_args += ['+{}={}'.format(key, value)]
else:
_args = args
pr_info("Running simulation")
utils.Launcher('./V' + self.top_module,
_args,
cwd=os.path.join(self.work_root, 'obj_dir'),
env=self.env).run()
def build_C(self, core, work_root, src_root):
args = ['-c']
args += ['-std=c99']
args += ['-I'+src_root]
args += ['-I'+os.path.join(src_root, core.sanitized_name, s) for s in core.verilator.include_dirs]
for src_file in core.verilator.src_files:
pr_info("Compiling " + src_file.name)
l = utils.Launcher('gcc',
args + [os.path.join(src_root, core.sanitized_name, src_file.name)],
cwd=work_root,
stderr = open(os.path.join(work_root, 'gcc.err.log'),'a'),
stdout = open(os.path.join(work_root, 'gcc.out.log'),'a'))
if Config().verbose:
pr_info(" C compilation working dir: " + work_root)
pr_info(" C compilation command: gcc " + ' '.join(args) + ' ' + os.path.join(src_root, core.sanitized_name, src_file.name))
l.run()
def run(self, args):
if not self.fusesoc_cli_parser:
self.plusargs = []
super(Verilator, self).run(args)
self.env = os.environ.copy()
self.env['CORE_ROOT'] = os.path.abspath(self.system.core_root)
self.env['BUILD_ROOT'] = os.path.abspath(self.build_root)
self.env['SIM_ROOT'] = os.path.abspath(self.sim_root)
if self.fusesoc_cli_parser:
_args = ['+' + s for s in self.plusargs]
else:
_args = args
pr_info("Running simulation")
utils.Launcher('./V' + self.top_module,
_args,
cwd=os.path.join(self.sim_root, 'obj_dir'),
env=self.env).run()
def run(self, args):
fusesoc_cli_parser = (self.system.verilator.cli_parser == 'fusesoc')
super(Verilator, self).run(args)
if fusesoc_cli_parser:
_args = []
for key, value in self.plusarg.items():
_args += ['+{}={}'.format(key, self._param_value_str(value))]
for key, value in self.cmdlinearg.items():
_args += ['--{}={}'.format(key, self._param_value_str(value))]
else:
_args = args
logger.info("Running simulation")
utils.Launcher('./V' + self.system.verilator.top_module,
_args,
cwd=self.work_root,
env = self.env).run()
def _verilate(self):
if self.src_type == 'systemC':
args = ['--sc']
else:
args = ['--cc']
args += ['-f', self.verilator_file]
args += ['--top-module', self.top_module]
args += ['--exe']
args += ['-LDFLAGS "']
args += [os.path.join(self.sim_root, s) for s in self.object_files]
args += ['-Wl,--start-group']
args += [l for l in self.libs]
args += ['-Wl,--end-group']
args += ['"']
args += ['-CFLAGS ' + '-I' + i for i in self.include_dirs]
args += [self.tb_toplevel]
args += self.verilator_options
self.verilator_root = os.getenv('VERILATOR_ROOT')
if self.verilator_root is None:
try:
output = subprocess.check_output(["which", "verilator"])
except subprocess.CalledProcessError:
print(
"VERILATOR_ROOT not set and there is no verilator program in your PATH"
)
exit(1)
print("VERILATOR_ROOT not set, fusesoc will use " + output)
cmd = 'verilator'
else:
cmd = os.path.join(self.verilator_root, 'bin', 'verilator')
cmd += ' ' + ' '.join(args)
l = utils.Launcher(cmd,
shell=True,
cwd=self.sim_root,
stderr=open(
os.path.join(self.sim_root, 'verilator.log'),
'w'))
print(l)
l.run()
def patch(self, dst_dir):
#FIXME: Use native python patch instead
patch_root = os.path.join(self.core_root, 'patches')
patches = self.main.patches
if os.path.exists(patch_root):
for p in sorted(os.listdir(patch_root)):
patches.append(os.path.join('patches', p))
for f in patches:
patch_file = os.path.abspath(os.path.join(self.core_root, f))
if os.path.isfile(patch_file):
logger.debug(" applying patch file: " + patch_file + "\n" +
" to: " + os.path.join(dst_dir))
try:
utils.Launcher('git', ['apply', '--unsafe-paths',
'--directory', os.path.join(dst_dir),
patch_file]).run()
except OSError:
print("Error: Failed to call external command 'patch'")
return False
return True
def _build(self, core, sim_root, src_root):
source_type = core.verilator.source_type
if source_type == 'C' or source_type == '':
self.build_C(core, sim_root, src_root)
elif source_type == 'CPP':
self.build_CPP(core, sim_root, src_root)
elif source_type == 'systemC':
self.build_SysC(core, sim_root, src_root)
else:
raise Source(core.verilator.source_type)
if core.verilator._object_files:
args = []
args += ['rvs']
args += [core.sanitized_name + '.a']
args += core.verilator._object_files
l = utils.Launcher('ar', args, cwd=sim_root)
if Config().verbose:
pr_info(" linker working dir: " + sim_root)
pr_info(" linker command: ar " + ' '.join(args))
l.run()
print()
def run(self, args):
if self.tool_options['mode'] == 'lint-only':
return
if self._fusesoc_parser():
self.parse_args(args, self.argtypes)
_args = []
for key, value in self.plusarg.items():
_args += ['+{}={}'.format(key, self._param_value_str(value))]
for key, value in self.cmdlinearg.items():
_args += ['--{}={}'.format(key, self._param_value_str(value))]
else:
_args = args
if 'pre_run' in self.hooks:
self._run_scripts(self.hooks['pre_run'])
logger.info("Running simulation")
utils.Launcher('./V' + self.toplevel,
_args,
cwd=self.work_root,
env=self.env).run()
self.run_post()
def build(self):
super(Icestorm, self).build()
utils.Launcher('make', cwd=self.work_root).run()
super(Icestorm, self).done()
def run(self, remaining):
args = ['--mode=jtag']
args += remaining
args += ['-o']
args += ['p;' + self.name.replace('.', '_') + '.sof']
utils.Launcher('quartus_pgm', args, cwd=self.work_root).run()
def run(self, args):
#TODO: Handle arguments parsing
utils.Launcher('./V' + self.top_module,
args,
cwd=os.path.join(self.sim_root, 'obj_dir')).run()
def build_main(self):
utils.Launcher('xtclsh', [os.path.join(self.work_root, self.name+'.tcl')],
cwd = self.work_root,
errormsg = "Failed to make FPGA load module").run()
def pgm(self, remaining):
args = ['--mode=jtag']
args += remaining
args += ['-o']
args += ['p;' + self.system.name + '.sof']
utils.Launcher('quartus_pgm', args, cwd=self.work_root).run()
def build(self, args):
super(Quartus, self).build(args)
utils.Launcher('make', cwd=self.work_root).run()
super(Quartus, self).done()
