def PC(in_, load, inc, reset):
"16-bit counter with load and reset controls."
out_ = deferred_wires(16)
choice1 = gates.mux16(out_, arithmetic.inc16(out_), inc)
choice2 = gates.mux16(choice1, in_, load)
choice3 = gates.mux16(choice2, (lo,) * 16, reset)
return resolve(out_, register(choice3, hi))
def PC(in_, load, inc, reset):
"16-bit counter with load and reset controls."
out_ = deferred_wires(16)
choice1 = gates.mux16(out_, arithmetic.inc16(out_), inc)
choice2 = gates.mux16(choice1, in_, load)
choice3 = gates.mux16(choice2, (lo, ) * 16, reset)
return resolve(out_, register(choice3, hi))
def CPU(inM, instruction, reset, sim=None):
"""The Central Processing unit (CPU). Inputs:
* inM from data memory
* instruction from program memory
* reset to restart from address 0.
Outputs:
* outM, writeM, addressM to data memory (for an instruction
writing to M).
* pc addressing program memory to fetch the next instruction.
"""
j3, j2, j1 = instruction[0:3]
d3, d2, d1 = instruction[3:6]
c6, c5, c4, c3, c2, c1 = instruction[6:12]
a_bit = instruction[12]
c_insn = instruction[15] & instruction[14] & instruction[13]
outM = deferred_wires(16)
a_mux = mux16(instruction, outM, c_insn)
a_reg = register(a_mux, ~instruction[15] | (c_insn & d1))
d_reg = register(outM, d2 & c_insn)
if sim:
sim.watch(a_mux, 'a_mux')
sim.watch(a_reg, 'A')
writeM = c_insn & d3
addressM = a_reg
y_mux = mux16(a_reg, inM, a_bit)
# XXX double-check alu x/y inputs
alu_out, alu_zr, alu_ng = alu(x=d_reg, y=y_mux,
zx=c1, nx=c2, zy=c3, ny=c4, f=c5, no=c6)
resolve(outM, alu_out)
pcinc = ~(j1 & alu_ng | j2 & alu_zr | j3 & ~alu_zr & ~alu_ng)
pc = PC(a_reg, ~pcinc, pcinc, reset)
return outM, writeM, addressM, pc
def alu(x, y, zx, nx, zy, ny, f, no):
"Return out, zr, ng."
assert (16, 16) == (len(x), len(y))
zeroes = (logsim.lo,) * 16
x0 = gates.mux16(x, zeroes, zx)
x1 = gates.mux16(x0, gates.not16(x0), nx)
y0 = gates.mux16(y, zeroes, zy)
y1 = gates.mux16(y0, gates.not16(y0), ny)
combo = gates.mux16(gates.and16(x1, y1),
add16(x1, y1),
f)
out = gates.mux16(combo, gates.not16(combo), no)
zr = ~or16way(out)
ng = out[-1]
assert 16 == len(out)
return out, zr, ng