def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# hdmi out 0
hdmi_out0_pads = platform.request("hdmi_out", 0)
dram_port = self.sdram.crossbar.get_port(
mode="read",
data_width=16,
clock_domain="pix",
reverse=True,
)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
hdmi_out0_pads,
dram_port,
mode="ycbcr422",
fifo_depth=4096,
)
self.hdmi_out0.submodules.i2c = i2c.I2C(hdmi_out0_pads)
# FIXME: Fix the HDMI out so this can be removed.
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command(
"""
NET "{pix0_clk}" TNM_NET = "GRPpix0_clk";
""",
pix0_clk=self.hdmi_out0.driver.clocking.cd_pix.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk)
def __init__(self, platform):
# TOFE board
tofe_pads = platform.request('tofe')
self.submodules.i2c = i2c.I2C(tofe_pads)
# Use a proper Tristate for the reset signal so the "pull up" works.
tofe_reset = TSTriple(1)
self.comb += [
tofe_reset.o.eq(0),
]
self.specials += [
tofe_reset.get_tristate(tofe_pads.rst),
]
self.submodules.rst = GPIOOut(tofe_reset.oe)
def __init__(self, platform):
self.submodules.mux = i2c.I2CMux(platform.request("opsis_i2c"))
self.submodules.master = i2c.I2C(self.mux.get_i2c_pads())
# Use a proper Tristate for the FX2 reset so the "pull up" works.
fx2_reset = TSTriple(1)
self.comb += [
fx2_reset.o.eq(0),
]
self.specials += [
fx2_reset.get_tristate(platform.request("fx2_reset")),
]
self.submodules.fx2_reset = GPIOOut(fx2_reset.oe)
self.submodules.fx2_hack = I2CShiftReg(self.mux.get_i2c_pads())
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
mode = "ycbcr422"
if mode == "ycbcr422":
dw = 16
elif mode == "rgb":
dw = 32
else:
raise SystemError("Unknown pixel mode.")
# hdmi in 0
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
)
self.submodules.hdmi_in0_freq = freq_measurement.FrequencyMeasurement(
self.hdmi_in0.clocking.clk_input, measure_period=self.clk_freq)
# hdmi in 1
hdmi_in1_pads = platform.request("hdmi_in", 1)
self.submodules.hdmi_in1 = HDMIIn(
hdmi_in1_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
)
self.submodules.hdmi_in1_freq = freq_measurement.FrequencyMeasurement(
self.hdmi_in1.clocking.clk_input, measure_period=self.clk_freq)
# hdmi out 0
hdmi_out0_pads = platform.request("hdmi_out", 0)
hdmi_out0_dram_port = self.sdram.crossbar.get_port(
mode="read",
data_width=dw,
clock_domain="hdmi_out0_pix",
reverse=True,
)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
hdmi_out0_pads,
hdmi_out0_dram_port,
mode=mode,
fifo_depth=4096,
)
self.hdmi_out0.submodules.i2c = i2c.I2C(hdmi_out0_pads)
# hdmi out 1 : Share clocking with hdmi_out0 since no PLL_ADV left.
hdmi_out1_pads = platform.request("hdmi_out", 1)
hdmi_out1_dram_port = self.sdram.crossbar.get_port(
mode="read",
data_width=dw,
clock_domain="hdmi_out1_pix",
reverse=True,
)
self.submodules.hdmi_out1 = VideoOut(
platform.device,
hdmi_out1_pads,
hdmi_out1_dram_port,
mode=mode,
fifo_depth=4096,
external_clocking=self.hdmi_out0.driver.clocking,
)
self.hdmi_out1.submodules.i2c = i2c.I2C(hdmi_out1_pads)
# all PLL_ADV are used: router needs help...
platform.add_platform_command("""INST crg_pll_adv LOC=PLL_ADV_X0Y0;""")
# FIXME: Fix the HDMI out so this can be removed.
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg_1.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
# We have CDC to go from sys_clk to pixel domain
platform.add_platform_command(
"""
NET "{pix0_clk}" TNM_NET = "GRPpix0_clk";
NET "{pix1_clk}" TNM_NET = "GRPpix1_clk";
""",
pix0_clk=self.hdmi_out0.driver.clocking.cd_pix.clk,
pix1_clk=self.hdmi_out1.driver.clocking.cd_pix.clk,
)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix.clk)
for name, value in sorted(self.platform.hdmi_infos.items()):
self.add_constant(name, value)
self.add_interrupt("hdmi_in0")
self.add_interrupt("hdmi_in1")
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# hdmi in 0
self.submodules.hdmi_in0 = HDMIIn(
platform.request("hdmi_in", 0),
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512)
self.submodules.hdmi_in0_freq = freq_measurement.FrequencyMeasurement(
self.hdmi_in0.clocking.clk_input, measure_period=self.clk_freq)
# hdmi in 1
self.submodules.hdmi_in1 = HDMIIn(
platform.request("hdmi_in", 1),
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512)
self.submodules.hdmi_in1_freq = freq_measurement.FrequencyMeasurement(
self.hdmi_in1.clocking.clk_input, measure_period=self.clk_freq)
# hdmi out 0
hdmi_out0_pads = platform.request("hdmi_out", 0)
self.submodules.hdmi_out0 = VideoOut(platform.device,
hdmi_out0_pads,
self.sdram.crossbar.get_port(
mode="read",
dw=16,
cd="hdmi_out0_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=4096)
self.hdmi_out0.submodules.i2c = i2c.I2C(hdmi_out0_pads)
# hdmi out 1 : Share clocking with hdmi_out0 since no PLL_ADV left.
hdmi_out1_pads = platform.request("hdmi_out", 1)
self.submodules.hdmi_out1 = VideoOut(
platform.device,
hdmi_out1_pads,
self.sdram.crossbar.get_port(mode="read",
dw=16,
cd="hdmi_out1_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=4096,
external_clocking=self.hdmi_out0.driver.clocking)
self.hdmi_out1.submodules.i2c = i2c.I2C(hdmi_out1_pads)
# all PLL_ADV are used: router needs help...
platform.add_platform_command("""INST crg_pll_adv LOC=PLL_ADV_X0Y0;""")
# FIXME: Fix the HDMI out so this can be removed.
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg_1.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
# We have CDC to go from sys_clk to pixel domain
platform.add_platform_command(
"""
NET "{pix0_clk}" TNM_NET = "GRPpix0_clk";
NET "{pix1_clk}" TNM_NET = "GRPpix1_clk";
""",
pix0_clk=self.hdmi_out0.driver.clocking.cd_pix.clk,
pix1_clk=self.hdmi_out1.driver.clocking.cd_pix.clk,
)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix.clk)
def __init__(self, platform,
firmware_ram_size=0x10000,
firmware_filename=None,
**kwargs):
clk_freq = 50*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("opsis", self.__class__.__name__[:8])
fx2_uart_pads = platform.request("serial_fx2")
sd_card_uart_pads = platform.request("serial_sd_card")
uart_pads = UARTSharedPads()
self.comb += [
# TX
fx2_uart_pads.tx.eq(uart_pads.tx),
sd_card_uart_pads.tx.eq(uart_pads.tx),
# RX
uart_pads.rx.eq(fx2_uart_pads.rx & sd_card_uart_pads.rx)
]
self.submodules.uart_phy = UARTPHY(uart_pads, self.clk_freq, 115200)
self.submodules.uart = uart.UART(self.uart_phy)
# self.submodules.opsis_eeprom_i2c = i2c.I2C(platform.request("opsis_eeprom"))
self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("opsis_eeprom"))
self.submodules.tofe_eeprom_i2c = i2c.I2C(platform.request("tofe_eeprom"))
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(platform.request("ddram"),
MT41J128M16(self.clk_freq),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
self.comb += [
self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb),
self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
self.specials += Keep(self.crg.cd_sys.clk)
platform.add_platform_command("""
NET "{sys_clk}" TNM_NET = "GRPsys_clk";
""", sys_clk=self.crg.cd_sys.clk)