Exemplos de reg_read1b em Python

Exemplo n.º 1

Arquivo: gbt_config_errclr_sf5.py Projeto: alacrities/GBT4FELIX

#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)

ch = 22 + 4
a = reg_read1b(RegAddr.REG_TOPBOT, ch)
reg_write1b(RegAddr.REG_TOPBOT, ch, 1 - a)

reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)

Exemplo n.º 2

Arquivo: gbt_config.py Projeto: alacrities/GBT4FELIX

if ch<12:
    ch=ch
else:
    ch=ch+4



# set TOPBOT & ODDEVEN to 0
reg_write1b(RegAddr.REG_TOPBOT,ch,0)
reg_write1b(RegAddr.REG_ODDEVEN,ch,0)

# check alignment status
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,1)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,0)
time.sleep(timewait)
ret=reg_read1b(RegAddr.REG_RX_ALIGNMENT_DONE,ch)
# ret=1 means alignment is finished

phase_cnt=10
oddeven=0

while phase_cnt != 0:
  #  for each topbot oddeven, there are 10 phases, totally 40 phases.
  #  print ret
    if ret==0:
        if phase_cnt>1:
	    phase_cnt = phase_cnt - 1
            # shift 1 phase
            reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
            reg_write32b(RegAddr.REG_RXSLIDE,0)
            reg_write32b(RegAddr.REG_RXSLIDE,2**ch)

Exemplo n.º 3

    ch = ch + 4

# RX GTH RST
#reg_write32b(RegAddr.REG_GTHRXRST,2**ch)
#time.sleep(0.1)
#reg_write32b(RegAddr.REG_GTHRXRST,0)

# RX ALIGNMENT
reg_write1b(RegAddr.REG_TOPBOT, ch, 0)
reg_write1b(RegAddr.REG_ODDEVEN, ch, 0)

reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 1)
#time.sleep(0.1)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 0)
time.sleep(timewait)
ret = reg_read1b(RegAddr.REG_RX_ALIGNMENT_DONE, ch)
phase_cnt = 10
oddeven = 0
while phase_cnt != 0:
    #  print "phase_cnt is "+str(phase_cnt)
    #  print ret
    if ret == 0:
        if phase_cnt > 1:
            phase_cnt = phase_cnt - 1
            reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
            reg_write32b(RegAddr.REG_RXSLIDE, 0)
            reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
            reg_write32b(RegAddr.REG_RXSLIDE, 0)
            reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 1)
            #           time.sleep(0.1)
            reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 0)

Exemplo n.º 4

Arquivo: gbt_config_master.py Projeto: alacrities/GBT4FELIX

# RX GTH RST
#reg_write32b(RegAddr.REG_GTHRXRST,2**ch)
#time.sleep(0.1)
#reg_write32b(RegAddr.REG_GTHRXRST,0)



# RX ALIGNMENT
reg_write1b(RegAddr.REG_TOPBOT,ch,0)
reg_write1b(RegAddr.REG_ODDEVEN,ch,0)

reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,1)
#time.sleep(0.1)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,0)
time.sleep(timewait)
ret=reg_read1b(RegAddr.REG_RX_ALIGNMENT_DONE,ch)
phase_cnt=10
oddeven=0
while phase_cnt != 0:
  #  print "phase_cnt is "+str(phase_cnt) 
  #  print ret
    if ret==0:
        if phase_cnt>1:
	    phase_cnt = phase_cnt - 1
            reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
            reg_write32b(RegAddr.REG_RXSLIDE,0)
            reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
            reg_write32b(RegAddr.REG_RXSLIDE,0)
	    reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,1)
 #           time.sleep(0.1)
	    reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,0)

Exemplo n.º 5

topbot_final = -1

if ch < 12:
    ch = ch
else:
    ch = ch + 4

# set TOPBOT & ODDEVEN to 0
reg_write1b(RegAddr.REG_TOPBOT, ch, 0)
reg_write1b(RegAddr.REG_ODDEVEN, ch, 0)

# check alignment status
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 1)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 0)
time.sleep(timewait)
ret = reg_read1b(RegAddr.REG_RX_ALIGNMENT_DONE, ch)
# ret=1 means alignment is finished

phase_cnt = 10
oddeven = 0

while phase_cnt != 0:
    #  for each topbot oddeven, there are 10 phases, totally 40 phases.
    #  print ret
    if ret == 0:
        if phase_cnt > 1:
            phase_cnt = phase_cnt - 1
            # shift 1 phase
            reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
            reg_write32b(RegAddr.REG_RXSLIDE, 0)
            reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)

Exemplo n.º 6

Arquivo: gbt_config_errclr_sf5.py Projeto: alacrities/GBT4FELIX

#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)



ch=22+4
a=reg_read1b(RegAddr.REG_TOPBOT,ch)
reg_write1b(RegAddr.REG_TOPBOT,ch,1-a)

reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)