Exemplo n.º 1
0
    def port_name(self, x):
        return ["P", "N"][x]

    def value_name(self):
        return "incomplete"

s = myvs()

# s._y[0] not yet. how to do that?
s._y[0]

print("mtest", s.max_nodes(), s.long_label())
s2 = s.clone()
print("mtest", s2.max_nodes(), s2.long_label())
# s.clone()

print("TT", type(s))
a = install_device("myvs", s)
# b = gnucap.command_installer("myvs", s)

gnucap.command("set lang=verilog")
gnucap.parse("resistor #(.r(1)) r(1 0)")
# gnucap.parse("vsource #(.dc(1)) s(1 0)")
gnucap.parse("myvs #() s(1 0)")
gnucap.command("list")
gnucap.command("print dc fourtytwo(s) i(r) v(s) nodeprobe(s) v(nodes)")
gnucap.command("dc r 1 3 .5")

print("done")
Exemplo n.º 2
0
    def clone(self):
        return __class__(self)

    def ac_iwant_matrix(self):
        pass

    def tr_iwant_matrix(self):
        pass

    def tr_probe_num(self, s):
        return 1.


d1 = mytype()
a = install_device("mytype", d1)


class dummy(ELEMENT):
    def custom(self):
        return 41

    def dev_type(self):
        return "not_reached"

    def clone(self):
        return mytype(self)


d2 = dummy()
b = install_device("dummy", d2)
Exemplo n.º 3
0
		else:
			ELEMENT.__init__(self, other)
		self.HACK=[]

	def custom(self):
		return 42

	def clone(self):
		print("somelt clone")
		x = mytype(self)
		self.HACK.append(x)
		x.__class__ = mytype
		return x

s = mytype()
d1 = install_device("mytype", s)

command("set lang verilog")
parse("mytype #() a();")
parse("resistor #() r(0,0);")

cl = CARD_LIST().card_list_()
print("tst")
for a in cl:
	print(a.long_label(), "..")
	if(isinstance(a, mytype)):
		print(".. is mytype")
		assert(42==a.custom())
		assert(isinstance(a, ELEMENT))

	if(isinstance(a, ELEMENT)):
Exemplo n.º 4
0
		return 0;

	def port_number(self):
		return 2
	def port_name(self,x):
		return ["P","N"][x]
	def value_name(self):
		return "incomplete"

s = somecomponent()
print("mtest", s.max_nodes(), s.long_label())
s2 = s.clone()
# s2.tr_begin()
print("mtest", s2.max_nodes(), s2.long_label())
# s.clone()

print("TT", type(s))
a = install_device("somecomp", s)
# b = gnucap.command_installer("somecomp2", s)

gnucap.command("set lang=verilog")
gnucap.parse("vsource #(.dc(1)) v(1 0)")
gnucap.parse("somecomp #() s(1 0)")
gnucap.command("list")
gnucap.command("print dc fourtytwo(s) v(s)")
gnucap.command("dc v 0 1 .5")
gnucap.command("print transient fourtytwo(s) v(s)")
gnucap.command("transient 0 1 .5")

print("done")
Exemplo n.º 5
0
            return self.tr_involts()
        elif s == "nodeprobe":
            return self._n[0].v0()
        return 0

    def port_number(self):
        return 2

    def port_name(self, x):
        return ["P", "N"][x]

    def value_name(self):
        return "incomplete"

s = pzsrc()
a = install_device("pzsrc", s)


###################################################
class mysim(SIM):
    def do_it(self, cmd, scope):
        self._scope = scope
        self.sim_().set_command_ac()
        self.setup(cmd)
        self.sim_().init()
        self.sim_().alloc_vectors()

        acx = self.sim_()._acx
        acx.reallocate()

        self._scope = scope