def configure(self, config):
# type: (Dict[Any, Any]) -> None
"Updates configuration from a dictionary"
_logger.debug("Updating with base config:\n%s", pformat(config))
builder_name = config.pop("builder", None)
if builder_name is not None:
builder_cls = getBuilderByName(builder_name)
else:
builder_cls = getPreferredBuilder()
_logger.debug("Builder class: %s", builder_cls)
self._builder = builder_cls(self.work_dir, self._database)
sources_added = self._database.configure(config, str(self.root_dir))
# Add VUnit
if not isinstance(self._builder, Fallback):
for path, library, flags in getVunitSources(self._builder):
self._database.addSource(path, library, flags, flags)
# Add the flags from the root config file last, it should overwrite
# values set by the included files
if config:
_logger.warning("Some configuration elements weren't used:\n%s",
pformat(config))
if sources_added:
self._handleUiInfo("Added {} sources".format(sources_added))
else:
self._handleUiInfo("No sources were added")
def test_SystemverilogOnlyBuilder(self, get_source_files,
find_rtl_sources):
get_source_files.side_effect = [[
SourceFile(name=_path("path_0.vhd"), library="libary_0"),
SourceFile(name=_path("path_1.vhd"), library="libary_1"),
]]
find_rtl_sources.return_value = [
Path(_path("some_header.vh")),
Path(_path("some_header.svh")),
]
builder = MagicMock()
builder.builder_name = "msim"
builder.file_types = {FileType.systemverilog}
self.assertTrue(foundVunit(), "Need VUnit for this test")
# Should only have VHDL files
sources = list(getVunitSources(builder))
get_source_files.assert_called_once()
find_rtl_sources.assert_called_once()
self.assertCountEqual(
sources,
{
(Path(_path("path_0.vhd")), "libary_0", ("-2008", )),
(Path(_path("path_1.vhd")), "libary_1", ("-2008", )),
(Path(_path("some_header.vh")), None, ()),
(Path(_path("some_header.svh")), None, ()),
},
)
def test_VerilogOnlyBuilder(self, meth):
builder = MagicMock()
builder.builder_name = "msim"
builder.file_types = {FileType.verilog}
self.assertTrue(foundVunit(), "Need VUnit for this test")
self.assertFalse(list(getVunitSources(builder)))
meth.assert_not_called()
def test_VhdlAndSystemverilogOnlyBuilder(self, vhdl_method, sv_method,
find_rtl_sources):
vhdl_method.side_effect = [[
SourceFile(name=_path("path_0.vhd"), library="libary_0"),
SourceFile(name=_path("path_1.vhd"), library="libary_1"),
]]
sv_method.side_effect = [[
SourceFile(name=_path("path_2.sv"), library="libary_2"),
SourceFile(name=_path("path_3.sv"), library="libary_3"),
]]
find_rtl_sources.return_value = [
Path(_path("some_header.vh")),
Path(_path("some_header.svh")),
]
builder = MagicMock()
builder.builder_name = "xvhdl"
builder.file_types = {FileType.vhdl, FileType.systemverilog}
self.assertTrue(foundVunit(), "Need VUnit for this test")
# Should only have VHDL files
sources = list(getVunitSources(builder))
vhdl_method.assert_called_once()
sv_method.assert_called_once()
self.assertCountEqual(
sources,
{
(Path(_path("path_0.vhd")), "libary_0", ()),
(Path(_path("path_1.vhd")), "libary_1", ()),
(Path(_path("path_2.sv")), "libary_2", ()),
(Path(_path("path_3.sv")), "libary_3", ()),
(Path(_path("some_header.vh")), None, ()),
(Path(_path("some_header.svh")), None, ()),
},
)
def test_VhdlBuilder(self, get_source_files):
get_source_files.side_effect = [[
SourceFile(name=_path("path_0.vhd"), library="libary_0"),
SourceFile(name=_path("path_1.vhd"), library="libary_1"),
]]
builder = MagicMock()
builder.builder_name = "msim"
builder.file_types = {FileType.vhdl}
self.maxDiff = None
self.assertTrue(foundVunit(), "Need VUnit for this test")
# Should only have VHDL files
sources = list(getVunitSources(builder))
get_source_files.assert_called_once()
self.assertCountEqual(
sources,
{
(Path(_path("path_0.vhd")), "libary_0", ("-2008", )),
(Path(_path("path_1.vhd")), "libary_1", ("-2008", )),
},
)
def test_VunitNotFound(self):
builder = MagicMock()
with disableVunit:
self.assertFalse(list(getVunitSources(builder)))
