def test_ExpandWithRecursiveWildcardsAndRelativePaths(self):
# type: (...) -> Any
"""
Recursive wildcards are only available on Python3, expected result will
be different but we're not porting it back
"""
config = {"sources": [p.join("**", "*.sv")]}
_logger.info("config:\n%s", pformat(config))
if six.PY3:
expected = (SourceEntry(Path(x), None, (), (), ()) for x in (
self.join("some_sv.sv"),
self.join("dir_0", "some_sv.sv"),
self.join("dir_0", "dir_1", "some_sv.sv"),
self.join("dir_2", "some_sv.sv"),
self.join("dir_2", "dir_3", "some_sv.sv"),
))
else:
expected = (SourceEntry(Path(x), None, (), (), ()) for x in (
self.join("dir_0", "some_sv.sv"),
self.join("dir_2", "some_sv.sv"),
))
self.assertCountEqual(flattenConfig(config, root_path=self.base_path),
expected)
def configure(self, root_config, root_path):
# type: (Dict[str, Any], str) -> int
"""
Handles adding sources, libraries and flags from a dict, unrolling and
flatenning references.
Returns the number of sources added.
"""
cnt = 0
for entry in flattenConfig(root_config, root_path):
self.addSource(
path=entry.path,
library=entry.library,
single_flags=entry.single_flags,
dependencies_flags=entry.dependencies_flags,
)
cnt += 1
return cnt
def test_ExpandWithFileWildcards(self):
# type: (...) -> Any
config = {
"sources": [
self.join("*.vhd"),
self.join("*", "some_v.v"),
self.join("*", "dir_1", "*.sv"),
]
}
_logger.info("config:\n%s", pformat(config))
self.assertCountEqual(
flattenConfig(config, root_path=self.base_path),
(SourceEntry(Path(x), None, (), (), ()) for x in (
self.join("some_vhd.vhd"),
self.join("dir_0", "some_v.v"),
self.join("dir_2", "some_v.v"),
self.join("dir_0", "dir_1", "some_sv.sv"),
)),
)
def test_FlattenConfigAndPreserveScopes(self):
incl_0 = self._path("incl_0.json")
incl_1 = self._path("incl_1.json")
# incl_2 = self._path("incl_2.json")
incl_0_cfg = _ConfigDict()
incl_0_cfg.include += [incl_1]
incl_0_cfg.sources += [
"src_0_0.vhd",
"src_0_1.v",
"src_0_2.sv",
# ("src_0_3.vhd", {"library": "some_library"}),
# ("src_0_4.vhd", {"flags": ("some_flag",)}),
# ("src_0_5.vhd", {"library": "lib", "flags": ("and_flag",)}),
("src_0_3.vhd", {
"library": "l_0_3"
}),
("src_0_4.vhd", {
"flags": ("f_0_4", )
}),
("src_0_5.vhd", {
"library": "l_0_5",
"flags": ("f_0_5", )
}),
]
incl_0_cfg.flags = {
FileType.vhdl: {
BuildFlagScope.all: ["vhdl/0/glob"],
BuildFlagScope.dependencies: ["vhdl/0/deps"],
BuildFlagScope.single: ["vhdl/0/single"],
},
FileType.verilog: {
BuildFlagScope.all: ["verilog/0/glob"],
BuildFlagScope.dependencies: ["verilog/0/deps"],
BuildFlagScope.single: ["verilog/0/single"],
},
FileType.systemverilog: {
BuildFlagScope.all: ["systemverilog/0/glob"],
BuildFlagScope.dependencies: ["systemverilog/0/deps"],
BuildFlagScope.single: ["systemverilog/0/single"],
},
}
incl_1_cfg = _ConfigDict()
incl_1_cfg.sources += [
self._path("src_1_0.vhd"),
"src_1_1.v",
"src_1_2.sv",
("src_1_3.vhd", {
"library": "l_1_3"
}),
(self._path("src_1_4.vhd"), {
"flags": ("f_1_4", )
}),
("src_1_5.vhd", {
"library": "l_1_5",
"flags": ("f_1_5", )
}),
]
incl_1_cfg.flags = {
FileType.vhdl: {
BuildFlagScope.all: ["vhdl/1/glob"],
BuildFlagScope.dependencies: ["vhdl/1/deps"],
BuildFlagScope.single: ["vhdl/1/single"],
},
FileType.verilog: {
BuildFlagScope.all: ["verilog/1/glob"],
BuildFlagScope.dependencies: ["verilog/1/deps"],
BuildFlagScope.single: ["verilog/1/single"],
},
FileType.systemverilog: {
BuildFlagScope.all: ["systemverilog/1/glob"],
BuildFlagScope.dependencies: ["systemverilog/1/deps"],
BuildFlagScope.single: ["systemverilog/1/single"],
},
}
json_dump(incl_0_cfg.toDict(), open(incl_0, "w"))
json_dump(incl_1_cfg.toDict(), open(incl_1, "w"))
result = list(flattenConfig(incl_0_cfg.toDict(), self.base_path))
_logger.info("Result:\n%s", pformat(result))
self.assertCountEqual(
result,
(
(
self._Path("src_0_0.vhd"),
None,
(),
("vhdl/0/glob", "vhdl/0/single"),
("vhdl/0/glob", "vhdl/0/deps"),
),
(
self._Path("src_0_1.v"),
None,
(),
("verilog/0/glob", "verilog/0/single"),
("verilog/0/glob", "verilog/0/deps"),
),
(
self._Path("src_0_2.sv"),
None,
(),
("systemverilog/0/glob", "systemverilog/0/single"),
("systemverilog/0/glob", "systemverilog/0/deps"),
),
(
self._Path("src_0_3.vhd"),
"l_0_3",
(),
("vhdl/0/glob", "vhdl/0/single"),
("vhdl/0/glob", "vhdl/0/deps"),
),
(
self._Path("src_0_4.vhd"),
None,
("f_0_4", ),
(
"vhdl/0/glob",
"vhdl/0/single",
),
("vhdl/0/glob", "vhdl/0/deps"),
),
(
self._Path("src_0_5.vhd"),
"l_0_5",
("f_0_5", ),
(
"vhdl/0/glob",
"vhdl/0/single",
),
("vhdl/0/glob", "vhdl/0/deps"),
),
(
self._Path("src_1_0.vhd"),
None,
(),
("vhdl/1/glob", "vhdl/1/single"),
("vhdl/1/glob", "vhdl/1/deps"),
),
(
self._Path("src_1_1.v"),
None,
(),
("verilog/1/glob", "verilog/1/single"),
("verilog/1/glob", "verilog/1/deps"),
),
(
self._Path("src_1_2.sv"),
None,
(),
("systemverilog/1/glob", "systemverilog/1/single"),
("systemverilog/1/glob", "systemverilog/1/deps"),
),
(
self._Path("src_1_3.vhd"),
"l_1_3",
(),
("vhdl/1/glob", "vhdl/1/single"),
("vhdl/1/glob", "vhdl/1/deps"),
),
(
self._Path("src_1_4.vhd"),
None,
("f_1_4", ),
(
"vhdl/1/glob",
"vhdl/1/single",
),
("vhdl/1/glob", "vhdl/1/deps"),
),
(
self._Path("src_1_5.vhd"),
"l_1_5",
("f_1_5", ),
(
"vhdl/1/glob",
"vhdl/1/single",
),
("vhdl/1/glob", "vhdl/1/deps"),
),
),
)