def recoverFromState(cls, state):
"""
Returns an object of cls based on a given state
"""
obj = super(ConfigParser, cls).__new__(cls)
# pylint: disable=protected-access
sources = state.pop('_sources')
obj.filename = state.pop('filename', None)
obj._timestamp = state.pop('_timestamp')
obj._lock = Lock()
obj._parms = state['_parms']
obj._parms['batch_build_flags'] = state['_parms']['batch_build_flags']
obj._parms['single_build_flags'] = state['_parms']['single_build_flags']
obj._parms['global_build_flags'] = state['_parms']['global_build_flags']
obj._sources = {}
for path, src_state in sources.items():
if src_state['filetype'] == 'vhdl':
obj._sources[path] = VhdlParser.recoverFromState(src_state)
else:
obj._sources[path] = VerilogParser.recoverFromState(src_state)
# pylint: enable=protected-access
return obj
def recoverFromState(cls, state):
"""
Returns an object of cls based on a given state
"""
obj = super(ConfigParser, cls).__new__(cls)
# pylint: disable=protected-access
sources = state.pop('_sources')
obj.filename = state.pop('filename', None)
obj._timestamp = state.pop('_timestamp')
obj._lock = Lock()
obj._parms = state['_parms']
obj._parms['batch_build_flags'] = state['_parms']['batch_build_flags']
obj._parms['single_build_flags'] = state['_parms'][
'single_build_flags']
obj._parms['global_build_flags'] = state['_parms'][
'global_build_flags']
obj._sources = {}
for path, src_state in sources.items():
if src_state['filetype'] == 'vhdl':
obj._sources[path] = VhdlParser.recoverFromState(src_state)
else:
obj._sources[path] = VerilogParser.recoverFromState(src_state)
# pylint: enable=protected-access
return obj
def test():
if it.BUILDER_NAME != "msim":
_logger.info("MSim only test")
return
source = VhdlParser(p.join(it.SOURCES_PATH, 'no_messages.sv'))
records, rebuilds = it.builder.build(source)
it.assertNotIn('E', [x['error_type'] for x in records],
'This source should not generate errors.')
it.assertEqual(rebuilds, [])
def test():
if it.BUILDER_NAME not in ('msim', 'ghdl', 'xvhdl'):
_logger.info("Test requires a builder")
return
source = VhdlParser(
p.join(it.SOURCES_PATH, 'source_with_error.vhd'))
records, rebuilds = it.builder.build(source, forced=True)
for record in records:
_logger.info(record)
if it.BUILDER_NAME == 'msim':
expected = [{
'line_number': '4',
'error_number': '1136',
'error_message': 'Unknown identifier "some_lib".',
'column': None,
'error_type': 'E',
'checker': 'msim'
}]
elif it.BUILDER_NAME == 'ghdl':
expected = [{
'line_number': '4',
'error_number': None,
'error_message': 'no declaration for "some_lib"',
'column': '5',
'error_type': 'E',
'checker': 'ghdl'
}]
elif it.BUILDER_NAME == 'xvhdl':
expected = [{
'line_number': '4',
'error_number': 'VRFC 10-91',
'error_message': 'some_lib is not declared',
'column': None,
'error_type': 'E',
'checker': 'xvhdl'
}]
it.assertEqual(len(records), 1)
it.assertTrue(
utils.samefile(records[0].pop('filename'), source.filename))
it.assertEquals(records, expected)
it.assertEqual(rebuilds, [])
def test():
path = p.join(VIM_HDL_EXAMPLES, 'basic_library', 'very_common_pkg.vhd')
project = StandaloneProjectBuilder()
source, remarks = project.getSourceByPath(path)
it.assertEquals(source, VhdlParser(path, library='undefined'))
if project.builder.builder_name in ('msim', 'ghdl', 'xvhdl'):
it.assertEquals(remarks, [{
'checker':
'hdlcc',
'line_number':
'',
'column':
'',
'filename':
'',
'error_number':
'',
'error_type':
'W',
'error_message':
'Path "%s" not found in project file' % p.abspath(path)
}])
else:
it.assertEquals(remarks, [])
def test():
it.source = VhdlParser(_FILENAME)
def test():
state = it.source.getState()
other = VhdlParser('other.vhd')
it.assertNotEqual(it.source, other, "Sources should not be equal")
def test():
source = VhdlParser(p.join(it.SOURCES_PATH, 'no_messages.vhd'))
records, rebuilds = it.builder.build(source)
it.assertNotIn('E', [x['error_type'] for x in records],
'This source should not generate errors.')
it.assertEqual(rebuilds, [])