def test_hdl_signal():
"""Test signals."""
my_sig = HDLSignal("reg", "signal_x", size=(7, 0))
print(my_sig.dumps())
_ = my_sig[3:1]
_ = my_sig[7]
yet_another = my_sig[2:]
_ = my_sig[:2]
print(yet_another.dumps())
_ = HDLSignal("reg", "sig", HDLVectorDescriptor(1, 0))
# exceptions
with pytest.raises(ValueError):
_ = HDLSignal("unknown", "sig", 1)
with pytest.raises(ValueError):
_ = HDLSignal("reg", "sig", -1)
with pytest.raises(ValueError):
_ = HDLSignal("reg", "sig", (1, 2, 3))
with pytest.raises(TypeError):
_ = HDLSignal("reg", "sig", "invalid")
_ = HDLSignalSlice(my_sig, HDLVectorDescriptor(1, 0))
with pytest.raises(TypeError):
_ = HDLSignalSlice(my_sig, "invalid")
def test_hdl_module():
"""Test modules."""
mod = HDLModule("my_module")
mod = HDLModule("my_module", [HDLModulePort("in", "myport", 8)])
mod = HDLModule("my_module",
params=[HDLModuleParameter("myparam", "integer", 0)])
expr = ast.parse("myparam-1", mode="eval")
vec = HDLVectorDescriptor(left_size=HDLExpression(expr), right_size=0)
mod = HDLModule(
"my_module",
ports=[HDLModulePort("in", "myport", vec)],
params=HDLModuleParameter("myparam", "integer", 0),
)
print(mod.dumps(evaluate=True))
_ = mod.get_parameter_scope()
_ = mod.get_full_scope()
_ = mod.get_param_names()
_ = mod.get_port_names()
# failures
with pytest.raises(TypeError):
mod = HDLModule("my_module", 0)
with pytest.raises(TypeError):
mod = HDLModule("my_module", [0])
with pytest.raises(TypeError):
mod = HDLModule("my_module", params=[0])
with pytest.raises(TypeError):
mod = HDLModule("my_module", params=0)
def __init__(self, direction, name, size=1):
"""Initialize.
Args
----
direction: str
Port direction
size: int, tuple or vector.HDLVectorDescriptor
Port description
name: str
Port name
"""
super().__init__(direction, name)
if isinstance(size, int):
# default is [size-1:0] / (size-1 downto 0)
if size < 0:
raise ValueError("only positive size allowed")
self.vector = HDLVectorDescriptor(size - 1, 0)
elif isinstance(size, (tuple, list)):
if len(size) != 2:
raise ValueError("invalid vector "
'dimensions: "{}"'.format(size))
self.vector = HDLVectorDescriptor(*size)
elif isinstance(size, HDLVectorDescriptor):
self.vector = size
elif isinstance(size, HDLExpression):
self.vector = HDLVectorDescriptor(left_size=size - 1)
else:
raise TypeError("size can only be of types: int, list or"
" vector.HDLVectorDescriptor")
# create internal signal
self.signal = HDLSignal(sig_type="comb", sig_name=name, size=size)
def visit_Subscript(self, node):
"""Visit Subscripts."""
if isinstance(node.value, ast.Name):
signal = self._signal_lookup(node.value.id)
if signal is None:
raise NameError('in "{}": signal "{}" not available in'
" current scope".format(
self._get_current_block(), node.value.id))
if isinstance(node.slice, ast.Index):
index = self.visit(node.slice.value)
vec = HDLVectorDescriptor(index, index)
return HDLSignalSlice(signal, vec)
elif isinstance(node.slice, ast.Slice):
if isinstance(node.slice.upper, ast.Constant):
upper = node.slice.upper.value
else:
upper = node.slice.upper
if isinstance(node.slice.lower, ast.Constant):
lower = node.slice.lower.value
else:
lower = node.slice.lower
return HDLSignalSlice(signal, [upper, lower])
elif isinstance(node.slice, ast.Constant):
if isinstance(node.slice.value, int):
vec = HDLVectorDescriptor(node.slice.value,
node.slice.value)
return HDLSignalSlice(signal, vec)
else:
raise TypeError("type {} not supported".format(
node.slice.value.__class__.__name__))
else:
raise TypeError("type {} not supported".format(
node.slice.__class__.__name__))
else:
raise TypeError("type {} not supported".format(
node.value.__class__.__name__))
def test_module_port():
"""Test ports."""
HDLModulePort("in", "myport", 3)
HDLModulePort("out", "myport", (2, 0))
HDLModulePort("inout", "myport", HDLVectorDescriptor(2, 0))
# fail cases
with pytest.raises(ValueError):
HDLModulePort("unknown", "myport", 0)
with pytest.raises(ValueError):
HDLModulePort("in", "myport", -1)
with pytest.raises(ValueError):
HDLModulePort("in", "myport", (2, 3, 0))
with pytest.raises(TypeError):
HDLModulePort("in", "myport", "INVALID")
class HDLModulePort(HDLAbsModulePort):
"""HDL Module port."""
def __init__(self, direction, name, size=1):
"""Initialize.
Args
----
direction: str
Port direction
size: int, tuple or vector.HDLVectorDescriptor
Port description
name: str
Port name
"""
super().__init__(direction, name)
if isinstance(size, int):
# default is [size-1:0] / (size-1 downto 0)
if size < 0:
raise ValueError("only positive size allowed")
self.vector = HDLVectorDescriptor(size - 1, 0)
elif isinstance(size, (tuple, list)):
if len(size) != 2:
raise ValueError("invalid vector "
'dimensions: "{}"'.format(size))
self.vector = HDLVectorDescriptor(*size)
elif isinstance(size, HDLVectorDescriptor):
self.vector = size
elif isinstance(size, HDLExpression):
self.vector = HDLVectorDescriptor(left_size=size - 1)
else:
raise TypeError("size can only be of types: int, list or"
" vector.HDLVectorDescriptor")
# create internal signal
self.signal = HDLSignal(sig_type="comb", sig_name=name, size=size)
def __repr__(self, eval_scope=None):
"""Get readable representation."""
return "{} {}{}".format(self.direction.upper(), self.name,
self.vector.dumps(eval_scope))
def __getitem__(self, index):
"""Emulate subscript."""
return HDLSignalSlice(self.signal, index)
def test_vector_descriptor():
"""Test vectors."""
# basic testing
vec = HDLVectorDescriptor(0, 0)
print(vec.dumps())
assert len(vec) == 1
vec = HDLVectorDescriptor(7)
# test failure modes
with pytest.raises(ValueError):
vec = HDLVectorDescriptor(-1, 0)
with pytest.raises(TypeError):
vec = HDLVectorDescriptor("1", 0)
with pytest.raises(TypeError):
vec = HDLVectorDescriptor(left_size=1, right_size="1")
with pytest.raises(TypeError):
vec = HDLVectorDescriptor(7, stored_value="a")
vec = HDLVectorDescriptor(8, stored_value=256)
left, right = vec.evaluate()
with pytest.raises(ValueError):
HDLVectorDescriptor(7, stored_value=256)