def _reg(self,
name: str,
dtype: HdlType = BIT,
def_val: Union[int, None, dict, list] = None,
clk: Union[RtlSignalBase, None, Tuple[RtlSignalBase,
OpDefinition]] = None,
rst: Optional[RtlSignalBase] = None) -> RtlSyncSignal:
"""
Create RTL FF register in this unit
:param def_val: s default value of this register,
if this value is specified reset signal of this component is used
to generate a reset logic
:param clk: optional clock signal specification,
(signal or tuple(signal, edge type (AllOps.RISING_EDGE/FALLING_EDGE)))
:param rst: optional reset signal specification
:note: rst/rst_n resolution is done from signal type,
if it is negated type the reset signal is interpreted as rst_n
:note: if clk or rst is not specified default signal
from parent unit instance will be used
"""
if clk is None:
clk = getClk(self)
if def_val is None:
# if no value is specified reset is not required
rst = None
elif rst is None:
rst = getRst(self)
if isinstance(dtype, HStruct):
container = HdlType_to_Interface(dtype)
container._loadDeclarations()
flattened_def_val = {}
_flatten_map(TypePath(), def_val, flattened_def_val)
for path, intf in container._fieldsToInterfaces.items():
if isinstance(intf, Signal):
_def_val = flattened_def_val.get(path, None)
intf._sig = self._reg(
"%s_%s" %
(name,
intf._getFullName(separator_getter=lambda x: "_")),
intf._dtype,
def_val=_def_val)
return container
elif isinstance(dtype, HArray):
raise NotImplementedError()
return self._ctx.sig(name,
dtype=dtype,
clk=clk,
syncRst=rst,
def_val=def_val)
def getRstn(self):
"""
lookup reset(n) signal on parent
"""
end = self.end
if end is None:
rst = getRst(self.parent)
else:
rst = end._getAssociatedRst()
if isinstance(rst._dtype, Bits) and rst._dtype.negated:
return rst
else:
return ~rst
def _reg(self,
name: str,
dtype: HdlType = BIT,
def_val: Union[int, None, dict, list] = None,
clk: Union[RtlSignalBase, None, Tuple[RtlSignalBase,
OpDefinition]] = None,
rst: Optional[RtlSignalBase] = None) -> RtlSyncSignal:
"""
Create RTL FF register in this unit
:param def_val: s default value of this register,
if this value is specified reset signal of this component is used
to generate a reset logic
:param clk: optional clock signal specification,
(signal or tuple(signal, edge type (AllOps.RISING_EDGE/FALLING_EDGE)))
:param rst: optional reset signal specification
:note: rst/rst_n resolution is done from signal type,
if it is negated type the reset signal is interpreted as rst_n
:note: if clk or rst is not specified default signal
from parent unit instance will be used
"""
if clk is None:
clk = getClk(self)
if def_val is None:
# if no value is specified reset is not required
rst = None
elif rst is None:
rst = getRst(self)
if isinstance(dtype, (HStruct, HArray)):
container = HdlType_to_Interface().apply(dtype)
_loadDeclarations(container, name)
_instanciate_signals(
container, clk, rst, def_val, NOT_SPECIFIED,
lambda name, dtype, clk, rst, def_val, nop_val: self._reg(
name, dtype, def_val=def_val, clk=clk, rst=rst))
container._parent = self
return container
else:
# primitive data type signal
return self._ctx.sig(name,
dtype=dtype,
clk=clk,
syncRst=rst,
def_val=def_val)
def _getAssociatedRst(self):
"""
If interface has associated rst(_n) return it otherwise
try to find rst(_n) on parent recursively
"""
a = self._associatedRst
if a is not None:
return a
p = self._parent
assert p is not None
if isinstance(p, UnitBase):
return getRst(p)
else:
return p._getAssociatedRst()