def test_mergable(self, N=10, ADDRESSES=[
0,
], randomized=False):
u = self.u
mem = AxiSimRam(u.m)
expected = {}
for a in ADDRESSES:
for i in range(N):
B_i = i % (u.CACHE_LINE_SIZE)
d = i << (B_i * 8)
m = 1 << B_i
u.w._ag.data.append((a, d, m))
v = expected.get(a, 0)
v = set_bit_range(v, B_i * 8, 8, i)
expected[a] = v
t = (N * len(ADDRESSES) + 10) * 3 * \
u.BUS_WORDS_IN_CACHE_LINE * CLK_PERIOD
if randomized:
#t *= 2
self.randomize_all()
self.runSim(t)
data = mem.getArray(0, u.CACHE_LINE_SIZE, max(ADDRESSES) + 1)
for a in ADDRESSES:
self.assertValEqual(
data[a], expected[a],
"%d: expected 0x%08x got 0x%08x, 0x%08x" %
(a, expected[a], data[a].val, data[a].vld_mask))
def test_write(self, N=20, randomize=False):
u = self.u
s_w = u.s_w
axi = u.m
m = AxiSimRam(axi=axi)
M_DW = axi.DATA_WIDTH
FRAME_WORD_CNT = ceil((u.S_ADDR_STEP) / M_DW)
w_data = [
i # self._rand.getrandbits(M_DW)
for i in range(N * FRAME_WORD_CNT)
]
# create data words for P4AppPort
wr_data = self.pack_words(w_data, M_DW, s_w.DATA_WIDTH)
for addr, frame in enumerate(wr_data):
s_w._ag.data.append((addr, frame))
if randomize:
axi_randomize_per_channel(self, axi)
self.runSim(N * FRAME_WORD_CNT * 10 * CLK_PERIOD)
w_m = mask(
s_w.DATA_WIDTH) if s_w.DATA_WIDTH < axi.DATA_WIDTH else mask(
axi.DATA_WIDTH)
addr = u.M_ADDR_OFFSET
inMem = m.getArray(addr, M_DW // 8, FRAME_WORD_CNT * N)
inMem = [None if v is None else v & w_m for v in inMem]
self.assertValSequenceEqual(inMem, w_data)
def test_with_mem(self, N=10, randomized=False):
u = self.u
mem = AxiSimRam(u.m)
u.w._ag.data.extend(
(i, 10 + i, mask(u.CACHE_LINE_SIZE)) for i in range(N))
if randomized:
self.randomize_all()
self.runSim((N + 10) * 3 * CLK_PERIOD * u.BUS_WORDS_IN_CACHE_LINE)
mem_val = mem.getArray(0, u.CACHE_LINE_SIZE, N)
self.assertValSequenceEqual(mem_val, [10 + i for i in range(N)])
def test_3x128(self, N=128):
u = self.u
m = AxiSimRam(axiAW=u.aw, axiW=u.w, axiB=u.b)
_mask = mask(self.DATA_WIDTH // 8)
data = [[self._rand.getrandbits(self.DATA_WIDTH) for _ in range(N)]
for _ in range(self.DRIVER_CNT)]
dataAddress = [
m.malloc(N * self.DATA_WIDTH // 8) for _ in range(self.DRIVER_CNT)
]
for di, _data in enumerate(data):
req = u.drivers[di].req._ag
wIn = u.drivers[di].w._ag
dataIt = iter(_data)
addr = dataAddress[di]
end = False
while True:
frameSize = self._rand.getrandbits(4) + 1
frame = []
try:
for _ in range(frameSize):
frame.append(next(dataIt))
except StopIteration:
end = True
if frame:
req.data.append(
Axi_datapumpTC.mkReq(self, addr,
len(frame) - 1))
wIn.data.extend([(d, _mask, i == len(frame) - 1)
for i, d in enumerate(frame)])
addr += len(frame) * self.DATA_WIDTH // 8
if end:
break
r = self.randomize
for d in u.drivers:
r(d.req)
r(d.w)
r(d.ack)
r(u.aw)
r(u.w)
r(u.b)
self.runSim(self.DRIVER_CNT * N * 40 * Time.ns)
for i, baseAddr in enumerate(dataAddress):
inMem = m.getArray(baseAddr, self.DATA_WIDTH // 8, N)
self.assertValSequenceEqual(inMem, data[i], f"driver:{i:d}")
def test_1024random(self):
u = self.u
req = u.driver._ag.req
wIn = u.driver.w._ag
dataMask = mask(u.DATA_WIDTH // 8)
m = AxiSimRam(axi=u.axi)
N = 1024
data = [self._rand.getrandbits(u.DATA_WIDTH) for _ in range(N)]
buff = m.malloc(N * (u.DATA_WIDTH // 8))
dataIt = iter(data)
end = False
addr = 0
while True:
frameSize = self._rand.getrandbits(
self.LEN_MAX_VAL.bit_length()) + 1
frame = []
try:
for _ in range(frameSize):
frame.append(next(dataIt))
except StopIteration:
end = True
if frame:
req.data.append(self.mkReq(addr, len(frame) - 1))
wIn.data.extend([(d, dataMask, i == len(frame) - 1)
for i, d in enumerate(frame)])
addr += len(frame) * u.DATA_WIDTH // 8
if end:
break
ra = self.randomize
ra(u.axi.aw)
ra(u.axi.b)
ra(u.driver.req)
ra(u.driver.ack)
ra(u.axi.w)
ra(u.driver.w)
self.runSim(N * 5 * CLK_PERIOD)
inMem = m.getArray(buff, u.DATA_WIDTH // 8, N)
self.assertValSequenceEqual(inMem, data)
def test_simpleTransfer(self):
u = self.u
regs = self.regs
N = 33
sampleData = [
self._rand.getrandbits(self.DATA_WIDTH) for _ in range(N)
]
m = AxiSimRam(u.axi)
blockPtr = m.malloc(self.DATA_WIDTH // 8 * N)
u.dataIn._ag.data.extend(sampleData)
regs.baseAddr.write(blockPtr)
regs.control.write(1)
self.runSim(N * 3 * CLK_PERIOD)
self.assertValSequenceEqual(
m.getArray(blockPtr, self.DATA_WIDTH // 8, N), sampleData)