def adjust_dest(self, index, dest, dest_str, op_len):
dest_type = ptx_declaration[dest_str]
if dest_type == '.pred':
return dest
else:
dest_len = int(dest_type[2:])
if dest_len > op_len:
return ila.sign_extend(dest, dest_len)
elif dest_len < op_len:
return dest[(dest_len - 1):0]
else:
return dest
def aux_dest(self, opcode, src_list, index):
dest = None
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
if opcode_name == 'mov':
dest = src_list[0]
if opcode_name == 'and':
dest = src_list[0] & src_list[1]
if opcode_name == 'cvta':
dest = src_list[0]
if opcode_name == 'shr':
dest = ila.ashr(src_list[0], src_list[1])
if opcode_name == 'add':
dest = src_list[0] + src_list[1]
if opcode_name == 'sub':
dest = src_list[0] - src_list[1]
if opcode_name == 'mul':
opcode_width = opcode_split[1]
op_len = int(opcode_split[2][1:])
if opcode_width == 'wide':
src0 = ila.sign_extend(src_list[0], op_len * 2)
src1 = ila.sign_extend(src_list[1], op_len * 2)
dest = src0 * src1
if opcode_name == 'setp':
opcode_cmp = opcode_split[1]
if opcode_cmp == 'ne':
dest = ila.ite(src_list[0] != src_list[1], self.pred_one, self.pred_zero)
if opcode_cmp == 'gt':
dest = ila.ite(src_list[0] > src_list[1], self.pred_one, self.pred_zero)
if opcode_cmp == 'lt':
dest = ila.ite(src_list[0] < src_list[1], self.pred_one, self.pred_zero)
if opcode_name == 'bar':
self.bar_inst[index] = self.bar_inst[index] | (self.pc_list[index] == self.current_pc)
if self.current_pc not in self.bar_list:
self.bar_list.append(self.current_pc)
#TODO: pc_next when bar
return dest
def createCheck(self):
st_set_file = 'st_set'
st_set_obj = open(st_set_file, 'r')
st_set = pickle.load(st_set_obj)
st_set_obj.close()
pred_map_file = 'pred_map'
pred_map_obj = open(pred_map_file, 'r')
pred_map = pickle.load(pred_map_obj)
pred_map_obj.close()
for pc in st_set.keys():
reg_name = st_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (1)), reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' % (1))
else:
operands[i] = ila.const(int(operand), reg_len)
check_reg = self.model.reg(reg_name + '_check_%d' % (pc),
instruction_format.LONG_REG_BITS)
self.check_registers.append(check_reg)
check_reg_next = operands[0]
for i in range(1, len(operands)):
check_reg_next = check_reg_next + operands[i]
self.model.set_next(
reg_name + '_check_%d' % (pc),
ila.ite(self.pc_list[1] == (pc), check_reg_next, check_reg))
en_check_reg = self.model.reg(reg_name + '_en_check_%d' % (pc), 1)
self.en_check_registers.append(en_check_reg)
en_check_reg_next = ila.const(0x1, 1)
pred_list = pred_map[pc]
for pred in pred_list:
pred_reg = self.model.getreg(pred + '_%d' % (1))
en_check_reg_next = ila.ite(pred_reg == ila.const(0x0, 1),
en_check_reg_next, en_check_reg)
self.model.set_next(
reg_name + '_en_check_%d' % (pc),
ila.ite(self.pc_list[1] == (pc), en_check_reg_next,
en_check_reg))
def get_reg_choices(reg):
rs1_val = rm.indexIntoGPR(rm.rs1)
rs2_val = rm.indexIntoGPR(rm.rs2)
rd_val = rm.indexIntoGPR(rm.rd)
rs_val = ila.choice('rs_sel', rs1_val, rs2_val)
shamt = ila.choice('shift_amout', rs2_val[4:0], rm.inst[24:20])
rs2_comb = ila.choice('rs2_or_immed', rs2_val,
ila.zero_extend(rm.immI, 32),
ila.sign_extend(rm.immI, 32))
addr = rs1_val + rm.immI
lw_val = ila.load(rm.mem, zext(addr[31:2]))
load_val = getSlice(lw_val, addr[1:0])
#load_dw = ila.loadblk(rm.mem, zext(addr[31:2]), 2 )
return ila.choice(
"x%d_next" % reg,
[
rm.generalRegList[
reg], # Remain the Same regardless of RD (i.e. S/SB instructions)
ila.ite(
rm.rd == reg, # Is this the destination register?
ila.choice(
"x%d" % reg,
[
rs1_val + rs2_comb, # RS1 + RS2
rs1_val - rs2_comb, # RS1 - RS2
rs1_val & rs2_comb, # AND
rs1_val | rs2_comb, # OR
rs1_val ^ rs2_comb, # XOR
ila.ite(
ila.slt(rs1_val, rs2_comb), # SLT
bv(1),
bv(0)),
ila.ite(ila.slt(rs1_val, rs2_comb), bv(0), bv(1)),
ila.ite(rs1_val < rs2_comb, bv(1), bv(0)),
rs1_val << zext(shamt), # sll
rs1_val >> zext(shamt), # srl
ila.ashr(rs1_val, zext(shamt)), # sra
rm.immU, # LUI
rm.immU + rm.pc, # AUIPC
rm.pc + bv(4), # JAL/JALR
load_val
#load_dw
]),
rm.generalRegList[reg]) # Remain the same
])
def instructionFetch(self):
self.inst = ila.load(self.mem,
ila.zero_extend(self.pc[31:2], MEM_ADDRESS_BITS))
self.opcode = self.inst[(REG_BITS - 1):OPCODE_BIT]
self.fetch_expr = self.inst
self.dest = self.inst[(OPCODE_BIT - 1):DST_BIT]
self.src1 = self.inst[(DST_BIT - 1):SRC0_BIT]
self.src2 = self.inst[(SRC0_BIT - 1):SRC1_BIT]
self.src3 = self.inst[(SRC1_BIT - 1):SRC2_BIT]
self.baseImm = ila.sign_extend(self.inst[(BASE_BIT - 1):0], PC_BITS)
self.branchPred = self.dest
self.predReg = self.indexIntoReg(self.branchPred)
self.branchImm = ila.zero_extend(self.inst[(DST_BIT - 1):BASE_BIT],
PC_BITS)
self.sreg1 = self.indexIntoReg(self.src1)
self.sreg2 = self.indexIntoReg(self.src2)
self.sreg3 = self.indexIntoReg(self.src3)
self.sregdest = self.indexIntoReg(self.dest)
def get_next_pc(self, index):
current_pc = self.pc_list[index]
seq_next = current_pc + 4
bar_stopped = ~((ila.is_bar_list[0]) & (ila.is_bar_list[1]))
bar_next = ila.ite(bar_stopped, current_pc, current_pc + 4)
bra_next = ila.sign_extend(self.imm_list[index],
instruction_format.PC_BITS)
pred_reg = self.get_pred_registers(self.pred_reg_list[index], index)
pc_next = ila.ite(
self.is_bra_list[index],
ila.ite(
self.pred_enable_list[index] == 0, bra_next,
ila.ite(
self.pred_enable_list[index] == 1,
ila.ite(pred_reg == ila.const(0x1, 1), bra_next, seq_next),
ila.ite(
self.pred_enable_list[index] == 2,
ila.ite(pred_reg == ila.const(0x1, 1), seq_next,
bra_next)))),
ila.ite(self.is_bar_list[index], bar_next,
ila.ite(current_pc >= max_pc, current_pc, seq_next)))
self.model.set_next('pc_%d' % (index), pc_next)
def instructionFetch(self):
self.inst = ila.load(
self.mem,
ila.zero_extend(self.pc[31:3],
instruction_format.MEM_ADDRESS_BITS))
self.opcode = self.inst[(instruction_format.OPCODE_BIT_TOP -
1):instruction_format.OPCODE_BIT_BOT]
self.fetch_expr = self.inst
self.dest = self.inst[(instruction_format.DST_BIT_TOP -
1):instruction_format.DST_BIT_BOT]
self.src1 = self.inst[(instruction_format.SRC0_BIT_TOP -
1):instruction_format.SRC0_BIT_BOT]
self.src2 = self.inst[(instruction_format.SRC1_BIT_TOP -
1):instruction_format.SRC1_BIT_BOT]
self.src3 = self.inst[(instruction_format.SRC2_BIT_TOP -
1):instruction_format.SRC2_BIT_BOT]
self.baseImm = ila.sign_extend(
self.inst[(instruction_format.BASE_BIT_TOP -
1):instruction_format.BASE_BIT_BOT],
instruction_format.PC_BITS)
self.branchPred = self.dest
self.predReg = self.indexIntoReg(self.branchPred)
self.branchImm = ila.zero_extend(
self.inst[(instruction_format.IMM_BIT_TOP -
1):instruction_format.IMM_BIT_BOT],
instruction_format.PC_BITS)
self.ldImm = ila.zero_extend(
self.inst[(instruction_format.IMM_BIT_TOP -
1):instruction_format.IMM_BIT_BOT],
instruction_format.PC_BITS)
self.stImm = ila.zero_extend(
self.inst[(instruction_format.IMM_BIT_TOP -
1):instruction_format.IMM_BIT_BOT],
instruction_format.PC_BITS)
self.sreg1 = self.indexIntoReg(self.src1)
self.sreg2 = self.indexIntoReg(self.src2)
self.sreg3 = self.indexIntoReg(self.src3)
self.sregdest = self.indexIntoReg(self.dest)
def aux_imm(self, operand_str, index, op_len):
if operand_str in ptx_declaration.keys():
operand = self.model.getreg(operand_str + '_%d' % (index))
operand_type = ptx_declaration[operand_str]
if operand_type == '.pred':
operand_length = instruction_format.PRED_REG_BITS
else:
operand_length = int(operand_type[2:])
if operand_length < op_len:
return ila.sign_extend(operand, op_len)
elif operand_length > op_len:
return operand[(op_len - 1) : 0]
else:
return operand
else:
operand_int = int(operand_str)
#print operand_int
if operand_int < 0:
operand_int = -operand_int
operand_int = (1 << (op_len - 1)) - operand_int + (1 << (op_len - 1))
#print operand_int
operand = self.model.const(operand_int, op_len)
return operand
def instructionFetch(self): self.instruction = ila.load(self.mem, ila.zero_extend(self.pc[31:2], MEM_ADDRESS_BITS)) self.isBranch = (self.instruction[31:28] == self.model.const(0b1111, 4)) self.branchOP = self.instruction[27:25] self.branchOffsetA = self.instruction[24:5] self.branchSrc = self.instruction[4:0] self.branchOffsetB = self.instruction[24:0] self.isRegReg = (self.instruction[31:29] == self.model.const(0b110,3)) self.rrType = self.instruction[28:26] self.rrOpcode = self.instruction[25:20] self.rrSrc2 = self.instruction[19:15] self.rrMask = self.instruction[14:10] self.rrDest = self.instruction[9:5] self.rrSrc1 = self.instruction[4:0] self.isImmediate = (self.instruction[31] == self.model.const(0b0, 1)) self.immType = self.instruction[30:29] self.immOpcode = self.instruction[28:24] self.immA = ila.zero_extend(self.instruction[23:15], SCALAR_REG_BITS) self.immB = ila.zero_extend(self.instruction[23:10], SCALAR_REG_BITS) self.immCup = self.instruction[23:10] self.immClow = self.instruction[4:0] self.immDest = self.instruction[9:5] self.immMask = self.instruction[14:10] self.imm = ila.ite(self.immType[1] == self.model.const(0b0, 1), ila.zero_extend(self.immB, SCALAR_REG_BITS), ila.ite(self.immType == self.model.const(0b10, 2), ila.zero_extend(ila.concat(self.immCup, self.immClow), SCALAR_REG_BITS), ila.ite(self.immType == self.model.const(0b11, 2), ila.zero_extend(self.immA, SCALAR_REG_BITS), ila.zero_extend(self.immA, SCALAR_REG_BITS)))) self.isMem = (self.instruction[31:30] == self.model.const(0b10, 2)) self.isLoad = self.instruction[29] self.memOpcode = self.instruction[28:25] self.memOffSetA = self.instruction[24:15] self.memOffSetB = self.instruction[24:10] self.memMask = self.instruction[14:10] self.memDest = self.instruction[9:5] self.memSrc = self.instruction[9:5] self.memPtr = self.instruction[4:0] self.memOffSet = ila.ite(self.memOpcode == self.model.const(0b1000, 4), ila.sign_extend(self.memOffSetA, SCALAR_REG_BITS), ila.ite(self.memOpcode == self.model.const(0b1110, 4), ila.sign_extend(self.memOffSetA, SCALAR_REG_BITS), ila.sign_extend(self.memOffSetB, SCALAR_REG_BITS))) self.isMask = (((self.rrType == self.model.const(0b010, 3)) | (self.rrType == self.model.const(0b101, 3))) & self.isRegReg) #need rewrite self.dest = self.instruction[9:5]
def create_data_race_element(self, access_set, log, lsg_update, atom):
if log == True:
suffix = 'log'
index = 0
else:
suffix = 'check'
index = 1
self.log_clean = ila.bool(False)
self.check_clean = ila.bool(False)
for pc in self.bar_sync_list:
self.log_clean = self.log_clean | ((self.pc_list[0] == pc) &
(self.pc_list[1] == pc))
self.check_clean = self.check_clean | ((self.pc_list[0] == pc) &
(self.pc_list[1] == pc))
ctaidx_0 = self.model.getreg('%ctaid.x_0')
ctaidx_1 = self.model.getreg('%ctaid.x_1')
ctaidy_0 = self.model.getreg('%ctaid.y_0')
ctaidy_1 = self.model.getreg('%ctaid.y_1')
self.log_clean = (self.log_clean) & ((ctaidx_0 == ctaidx_1) &
(ctaidy_0 == ctaidy_1))
self.check_clean = (self.check_clean) & ((ctaidx_0 == ctaidx_1) &
(ctaidy_0 == ctaidy_1))
for pc in access_set.keys():
reg_name = access_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
print operands
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (index)),
reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' %
(index))
else:
operands[i] = self.aux_imm(operand, 0, reg_len)
access_reg_next = operands[0]
for i in range(1, len(operands)):
access_reg_next = access_reg_next + operands[i]
en_access_reg_next = ila.const(0x1, 1)
en_access_reg_clear = ila.const(0x0, 1)
if log:
self.log_register_next = ila.ite(
(self.pc_list[0] == pc) & (self.arb_list[index] == 1),
access_reg_next, self.log_register_next)
self.en_log_register_next = ila.ite(
(self.pc_list[0] == pc) & (self.arb_list[index] == 1),
en_access_reg_next, self.en_log_register_next)
self.lsg_log_register_next = ila.ite(
(self.pc_list[0] == pc) & (self.arb_list[index] == 1),
lsg_update, self.lsg_log_register_next)
self.mflag_log_register_next_cond = (
(self.arb_list[index] == 1) &
(self.pc_list[0]
== pc)) | self.mflag_log_register_next_cond
if atom:
self.log_atom_flag_register_next = ila.ite(
(self.pc_list[0] == pc) & (self.arb_list[index] == 1),
ila.const(0x1, 1), self.log_atom_flag_register_next)
else:
self.log_atom_flag_register_next = ila.ite(
(self.pc_list[0] == pc) & (self.arb_list[index] == 1),
ila.const(0x0, 1), self.log_atom_flag_register_next)
else:
self.check_register_next = ila.ite(
(self.pc_list[1] == pc) & (self.arb_list[index] == 1),
access_reg_next, self.check_register_next)
self.en_check_register_next = ila.ite(
(self.pc_list[1] == pc) & (self.arb_list[index] == 1),
en_access_reg_next, self.en_check_register_next)
self.lsg_check_register_next = ila.ite(
(self.pc_list[1] == pc) & (self.arb_list[index] == 1),
lsg_update, self.lsg_check_register_next)
self.mflag_check_register_next_cond = (
(self.arb_list[index] == 1) &
(self.pc_list[1]
== pc)) | self.mflag_check_register_next_cond
if atom:
self.check_atom_flag_register_next = ila.ite(
(self.pc_list[1] == pc) & (self.arb_list[index] == 1),
ila.const(0x1, 1), self.check_atom_flag_register_next)
else:
self.check_atom_flag_register_next = ila.ite(
(self.pc_list[1] == pc) & (self.arb_list[index] == 1),
ila.const(0x0, 1), self.check_atom_flag_register_next)
if log:
self.en_log_register_next = ila.ite(self.log_clean,
ila.const(0x0, 1),
self.en_log_register_next)
else:
self.en_check_register_next = ila.ite(self.check_clean,
ila.const(0x0, 1),
self.en_check_register_next)
def main():
c = ila.Abstraction("test")
# n = ila.Node()
# test on boolOp
top = c.bool(True)
bot = c.bool(False)
Band = (top & bot) # 0
Bor = (top | bot) # 1
Bxor = (Band ^ Bor) # 1
Bnor = ila.nor(Band, Bor) # 0
Bxnor = ila.xnor(Bxor, Bnor) # 0
Bnand = ila.nand(Bnor, Bxnor) # 1
nBnor = ~Bnor # 1
assert c.areEqual(nBnor, top)
b1 = c.bit('b1')
b2 = c.bit('b2')
b3 = c.bit('b3')
b4 = (b1 & b2) ^ b3
b5 = ila.xnor(ila.nand(b1, b2), b3)
assert c.areEqual(b4, b5)
b6 = ila.ite(b1, b2, b3)
b7 = (b1 & b2) | (~b1 & b3)
assert c.areEqual(b6, b7)
# test on bitvectorOp
x = c.reg('x', 8)
y = c.reg('y', 8)
c0 = c.const(0, 8)
c1 = c.const(1, 8)
c2 = c.const(2, 8)
c4 = c.const(4, 8)
c6 = c.const(6, 8)
c8 = c.const(8, 8)
v1 = (x == c4)
v2 = x << 1
v3 = c4 << 1
assert c.areEqual(c8, v3)
assert c.areEqual(c8, (c4 + c4))
assert c.areEqual(c4, (c8 - c4))
assert c.areEqual(c8, (c4 * c2))
assert c.areEqual(c4, (c8 / c2))
v4 = ila.ite(v1, v2, v3) # 8
assert c.areEqual(v4, c8)
assert c.areEqual(v4, v3)
assert c.areEqual(v4, (4 + c4))
assert c.areEqual(-c4, (c4 - 8))
assert c.areEqual(v4, (2 * c4))
assert c.areEqual(v4 >> 2, (v3 / c2) - 2)
assert c.areEqual(c8 % 5, 7 % (1 << c2))
assert c.areEqual( (x < y) ^ (y <= x), (x == y) | (x != y) )
assert c.areEqual( (x > y) | (x == y) | ~(x >= y), top )
assert c.areEqual( ~x ^ x, y ^ ~y)
assert c.areEqual( ~x, ila.nand(x, x) )
v5 = ~ila.nor(c2, c4) # 00000110
assert c.areEqual( ~v5, ila.xnor(c4, c2))
v6 = c2 - c4 # 11111110
v7 = 3 - c8 # 11111011
v8 = ~(c2 - 2) # 11111111
assert c.areEqual( v8, ~c0)
assert c.areEqual( v8 - 1, v6)
assert c.areEqual( c4 + c1, -v7) # 00000101
assert c.areEqual( ila.sdiv(c4, c2), c2)
assert c.areEqual( ila.sdiv(-c4, c2), -c2)
assert c.areEqual( ila.sdiv(v5, -4), -c1)
assert c.areEqual( ila.srem(v5, -4), c2)
# -6 = -4 * 1 + -2 ??
assert c.areEqual( ila.sdiv(-6, -c4), c1)
assert c.areEqual( ila.srem(-v5, -c4), -c2)
assert c.areEqual( x - ila.srem(x, y), ila.sdiv(x, y) * y )
assert c.areEqual( x - x % y, (x / y) * y )
assert c.areEqual( ila.ashr(v6, 1), v8)
assert c.areEqual( ila.slt(v7, v6), top)
s1 = c.const(1, 4)
s2 = c.const(2, 4)
v9 = ila.concat(s1, s2) # 00010010
v10 = (c1 << 4) + c2
assert c.areEqual(v9, v10)
v11 = ila.rrotate(v9, 2) # 10000100
v12 = ila.lrotate(v9, 6)
assert c.areEqual(v11, v12)
s3 = c.const(9, 4)
v13 = v9[4:1]
assert c.areEqual(s3, v13)
v14 = x[3:0]
v15 = y[7:4]
v16 = ila.concat(v15, v14)
v17 = ((x << 4) >> 4) + ((y >> 4) << 4)
assert c.areEqual(v16, v17)
# imply
v18 = ila.slt(x, 5)
v19 = ila.sge(x, 5)
c.areEqual(ila.implies(v18, ~v19), top)
#nonzero & bool ite
v20 = ila.ite( ila.nonzero(x), (x<7), ~(x>=7) )
assert c.areEqual(v20, (x!=7) & ~(x>7))
assert c.areEqual(ila.nonzero(c4), top)
#add nonzero to ite
assert c.areEqual( ila.ite(ila.nonzero(c2), top, bot), top)
assert c.areEqual( ila.ite(ila.nonzero(c0), top, bot), bot)
# zero/sign extend
short = c4[3:0]
recover = ila.zero_extend(short, 8)
assert c.areEqual(recover, c4)
longC4 = c.const(4, 16)
nlongC4 = -longC4
nshortC4 = -c4
extNS4 = ila.sign_extend(nshortC4, 16)
assert c.areEqual(nlongC4, extNS4)
# extract/slice with var
v21 = c0[3:0]
v21r = ila.zero_extend(v21, 8)
assert c.areEqual(c0, v21r)
# v14 = x[3:0]
v14ex = ila.zero_extend(v14, 8)
v14re = (x << 4) >> 4
assert c.areEqual(v14ex, v14re)
# v15 = y[7:4]
v15ex = ila.zero_extend(v15, 8)
v15re = (y >> 4)
assert c.areEqual(v15ex, v15re)
"""
v21 = ila.extractIV(x, 3, c0)
v22 = ila.extractVI(y, c4+3, 4)
assert c.areEqual(v14ex, v21)
assert c.areEqual(v15ex << 4, v22 << 4)
v23 = v21 + (v22 << 4)
assert c.areEqual(v23, v16)
v24 = ila.extractVV(c8, c8-1, c0)
assert c.areEqual(v24, c8)
v25 = ila.extractVV(x, c8-1, c4)
v26 = ila.zero_extend(x[7:4], 8)
assert c.areEqual(v25, v26)
# slice one bit
bv1 = c.const(1, 1)
s1 = ila.get_bit(c1, c0)
assert c.areEqual(bv1, s1)
"""
z = x & x
bx = y[x]
bz = y[z]
assert c.areEqual(bx, bz)
bx = c8[x]
by = c8[y]
inv = ila.implies(x == y, bx == by)
assert c.areEqual(inv, top)
dum = ila.ite(b1, bx, by)
shd = ila.implies(x == y, dum == bx)
assert c.areEqual(shd, top)
assert c.areEqual(c6[1], c6[2])
assert c.areEqual(c6[4], c6[c0])
def vreg_nxt(self, regNo, laneNo):
ssreg1 = self.indexToSGPR(self.rrSrc1)
ssreg2 = self.indexToSGPR(self.rrSrc2)
vsreg1 = self.indexToVGPR(self.rrSrc1, self.model.const(laneNo, SCALAR_REG_BITS))
vsreg2 = self.indexToVGPR(self.rrSrc2, self.model.const(laneNo, SCALAR_REG_BITS))
mask = self.indexToSGPR(self.rrMask)
#load instruction
addr = self.indexToSGPR(self.memPtr) + ila.sign_extend(self.memOffSet, SCALAR_REG_BITS)
load_val = ila.load(self.mem, ila.zero_extend(addr[31:2], PC_BITS))
return ila.ite(self.dest == regNo,
ila.ite(self.isRegReg,
ila.ite(self.rrType == self.model.const(0b001, 3),
ila.ite(self.rrOpcode == NyEncoding.ADD_I, vsreg1 + ssreg2,
ila.ite(self.rrOpcode == NyEncoding.SUB_I, vsreg1 - ssreg2,
ila.ite(self.rrOpcode == NyEncoding.AND, vsreg1 & ssreg2,
ila.ite(self.rrOpcode == NyEncoding.OR, vsreg1 | ssreg2,
ila.ite(self.rrOpcode == NyEncoding.MULH_I, vsreg1 * ssreg2, self.vector_registers[regNo][laneNo]))))),
ila.ite(self.rrType == self.model.const(0b100, 3),
ila.ite(self.rrOpcode == NyEncoding.ADD_I, vsreg1 + vsreg2,
ila.ite(self.rrOpcode == NyEncoding.SUB_I, vsreg1 - vsreg2,
ila.ite(self.rrOpcode == NyEncoding.AND, vsreg1 & vsreg2,
ila.ite(self.rrOpcode == NyEncoding.OR, vsreg1 | vsreg2,
ila.ite(self.rrOpcode == NyEncoding.MULH_I, vsreg1 * vsreg2, self.vector_registers[regNo][laneNo]))))),
ila.ite(self.rrType == self.model.const(0b010, 3),
ila.ite(mask[laneNo] == self.model.const(0b0, 1), self.vector_registers[regNo][laneNo],
ila.ite(self.rrOpcode == NyEncoding.ADD_I, vsreg1 + ssreg2,
ila.ite(self.rrOpcode == NyEncoding.SUB_I, vsreg1 - ssreg2,
ila.ite(self.rrOpcode == NyEncoding.AND, vsreg1 & ssreg2,
ila.ite(self.rrOpcode == NyEncoding.OR, vsreg1 | ssreg2,
ila.ite(self.rrOpcode == NyEncoding.MULH_I, vsreg1 * ssreg2, self.vector_registers[regNo][laneNo])))))),
ila.ite(self.rrType == self.model.const(0b101, 3),
ila.ite(mask[laneNo] == self.model.const(0b0, 1), self.vector_registers[regNo][laneNo],
ila.ite(self.rrOpcode == NyEncoding.ADD_I, vsreg1 + vsreg2,
ila.ite(self.rrOpcode == NyEncoding.SUB_I, vsreg1 - vsreg2,
ila.ite(self.rrOpcode == NyEncoding.AND, vsreg1 & vsreg2,
ila.ite(self.rrOpcode == NyEncoding.OR, vsreg1 | vsreg2,
ila.ite(self.rrOpcode == NyEncoding.MULH_I, vsreg1 * vsreg2, self.vector_registers[regNo][laneNo])))))),
self.vector_registers[regNo][laneNo])
))),
ila.ite(self.isImmediate,
ila.ite(self.immType == self.model.const(0b01, 2),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.ADD_I, vsreg1 + self.immB,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.SUB_I, vsreg1 - self.immB,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.AND, vsreg1 & self.immB,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.OR, vsreg1 | self.immB,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.MULH_I, vsreg1 * self.immB,
self.vector_registers[regNo][laneNo]))))),
ila.ite(self.immType == self.model.const(0b11, 2),
ila.ite(mask[laneNo] == self.model.const(0b0, 1), self.vector_registers[regNo][laneNo],
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.ADD_I, vsreg1 + self.immA,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.SUB_I, vsreg1 - self.immA,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.AND, vsreg1 & self.immA,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.OR, vsreg1 | self.immA,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.MULH_I, vsreg1 * self.immA,
self.vector_registers[regNo][laneNo])))))),
self.vector_registers[regNo][laneNo]),
),
ila.ite(self.isLoad == self.model.const(0b1, 1), self.vector_registers[regNo][laneNo], self.vector_registers[regNo][laneNo])
)),
self.vector_registers[regNo][laneNo])
def sreg_nxt(self, regNo):
sreg1 = self.indexToSGPR(self.rrSrc1)
sreg2 = self.indexToSGPR(self.rrSrc2)
#load instruction
addr = self.indexToSGPR(self.memPtr) + ila.sign_extend(self.memOffSet, SCALAR_REG_BITS)
load_val = ila.load(self.mem, ila.zero_extend(addr[31:2], MEM_ADDRESS_BITS))
return ila.ite(self.dest == regNo,\
ila.ite(self.isRegReg,
ila.ite(self.rrType == self.model.const(0b000, 3),
ila.ite(self.rrOpcode == NyEncoding.ADD_I, sreg1 + sreg2,
ila.ite(self.rrOpcode == NyEncoding.SUB_I, sreg1 - sreg2,
ila.ite(self.rrOpcode == NyEncoding.AND, sreg1 & sreg2,
ila.ite(self.rrOpcode == NyEncoding.OR, sreg1 | sreg2,
ila.ite(self.rrOpcode == NyEncoding.MULH_I, self.auxMull_i(sreg1, sreg2),
ila.ite(self.rrOpcode == NyEncoding.MULH_U, self.auxMulh_u(sreg1, sreg2),
ila.ite(self.rrOpcode == NyEncoding.ASHR, ila.ashr(sreg1, sreg2[4:0]),
ila.ite(self.rrOpcode == NyEncoding.SHR, sreg1 >> sreg2[4:0],
ila.ite(self.rrOpcode == NyEncoding.SHL, sreg1 << sreg2[4:0],
ila.ite(self.rrOpcode == NyEncoding.CLZ, self.aux_clz(sreg2),
ila.ite(self.rrOpcode == NyEncoding.CTZ, self.aux_ctz(sreg2),
ila.ite(self.rrOpcode == NyEncoding.MOVE, sreg2,
ila.ite(self.rrOpcode == NyEncoding.CMPEQ_I, ila.ite(sreg1 == sreg2, self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(self.rrOpcode == NyEncoding.CMPNE_I, ila.ite(sreg1 != sreg2, self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(self.rrOpcode == NyEncoding.CMPGT_I, ila.ite(self.auxCmpgt_i(sreg1, sreg2) == self.getConstOne(), self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(self.rrOpcode == NyEncoding.CMPGE_I, ila.ite(self.auxCmpge_i(sreg1, sreg2) == self.getConstOne(), self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(self.rrOpcode == NyEncoding.CMPLT_I, ila.ite(self.auxCmplt_i(sreg1, sreg2) == self.getConstOne(), self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(self.rrOpcode == NyEncoding.CMPLE_I, ila.ite(self.auxCmple_i(sreg1, sreg2) == self.getConstOne(), self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(self.rrOpcode == NyEncoding.CMPGT_U, ila.ite(sreg1 > sreg2, self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(self.rrOpcode == NyEncoding.CMPGE_U, ila.ite(sreg1 < sreg2, self.const(0b0, SCALAR_REG_BITS), self.const(0xffff, SCALAR_REG_BITS)),
ila.ite(self.rrOpcode == NyEncoding.CMPLT_U, ila.ite(sreg1 < sreg2, self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(self.rrOpcode == NyEncoding.CMPLE_U, ila.ite(sreg1 > sreg2, self.const(0b0, SCALAR_REG_BITS), self.const(0xffff,SCALAR_REG_BITS)),
self.scalar_registers[regNo]))))))))))))))))))))))
, self.scalar_registers[regNo]),\
ila.ite(self.isImmediate,
ila.ite(self.immType == self.model.const(0b00, 2),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.ADD_I, sreg1 + self.immB,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.SUB_I, sreg1 - self.immB,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.AND, sreg1 & self.immB,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.OR, sreg1 | self.immB,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.MULH_I, self.auxMull_i(sreg1, self.immB),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.MULL_I, self.auxMulh_u(sreg1, self.immB),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.ASHR, ila.ashr(sreg1, self.immB[4:0]),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.SHR, sreg1 >> self.immB[4:0],
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.SHL, sreg1 << self.immB[4:0],
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CLZ, sreg1, self.aux_clz(self.immB),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CTZ, sreg1, self.aux_ctz(self.immB),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.MOVE, self.immB,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CMPEQ_I, ila.ite(sreg1 == self.immB, self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CMPNE_I, ila.ite(sreg1 != self.immB, self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CMPGT_I, ila.ite(self.auxCmpgt_i(sreg1, self.immB) == self.getConstOne(), self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CMPGE_I, ila.ite(self.auxCmpge_i(sreg1, self.immB) == self.getConstOne(), self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CMPLT_I, ila.ite(self.auxCmplt_i(sreg1, self.immB) == self.getConstOne(), self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CMPLE_I, ila.ite(self.auxCmple_i(sreg1, self.immB) == self.getConstOne(), self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CMPGT_U, ila.ite(sreg1 > self.immB, self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CMPGE_U, ila.ite(sreg1 < self.immB, self.const(0b0, SCALAR_REG_BITS), self.const(0xffff, SCALAR_REG_BITS)),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CMPLT_U, ila.ite(sreg1 < self.immB, self.const(0xffff, SCALAR_REG_BITS), self.const(0b0, SCALAR_REG_BITS)),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.CMPLE_U, ila.ite(sreg1 > self.immB, self.const(0b0, SCALAR_REG_BITS), self.const(0xffff,SCALAR_REG_BITS)),
self.scalar_registers[regNo])))))))))))))))))))))),\
ila.ite(self.immType == self.model.const(0b10, 2),
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.ADD_I, sreg1 + self.immA,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.SUB_I, sreg1 - self.immA,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.AND, sreg1 & self.immA,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.OR, sreg1 | self.immA,
ila.ite(ila.zero_extend(self.immOpcode, 6) == NyEncoding.MULH_I, sreg1 * sreg2, self.scalar_registers[regNo]))))),\
self.scalar_registers[regNo])),\
ila.ite(self.isLoad == self.model.const(0b1, 1), self.scalar_registers[regNo], self.scalar_registers[regNo]))),\
self.scalar_registers[regNo])
def create_data_race_element(self, access_set, pred_map, log):
if log == True:
suffix = 'log'
index = 0
else:
suffix = 'check'
index = 1
bar_pred_map_obj = open('bar_pred_map', 'r')
bar_pred_map = pickle.load(bar_pred_map_obj)
bar_pred_map_obj.close()
self.log_clean = ila.bool(False)
self.check_clean = ila.bool(False)
for pc in self.bar_list:
bar_pred_list = bar_pred_map[pc]
bar_pred = ila.bool(True)
for bar_pred_name in bar_pred_list:
bar_pred_reg = self.model.getreg(bar_pred_name + '_%d' %
(index))
bar_pred = bar_pred & (bar_pred_reg == ila.const(0x0, 1))
self.log_clean = self.log_clean | ((self.pc_list[0] == pc) &
(bar_pred))
self.check_clean = self.check_clean | ((self.pc_list[0] == pc) &
(bar_pred))
for pc in access_set.keys():
reg_name = access_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (index)),
reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' %
(index))
else:
operands[i] = ila.const(int(operand), reg_len)
access_reg = self.model.reg(reg_name + '_%s_%d' % (suffix, pc),
instruction_format.LONG_REG_BITS)
if log:
self.log_registers.append(access_reg)
else:
self.check_registers.append(access_reg)
access_reg_next = operands[0]
for i in range(1, len(operands)):
access_reg_next = access_reg_next + operands[i]
self.model.set_next(
reg_name + '_%s_%d' % (suffix, pc),
ila.ite(self.pc_list[index] == (pc), access_reg_next,
access_reg))
en_access_reg = self.model.reg(
reg_name + '_en_%s_%d' % (suffix, pc), 1)
if log:
self.en_log_registers.append(en_access_reg)
else:
self.en_check_registers.append(en_access_reg)
en_access_reg_next = ila.const(0x1, 1)
en_access_reg_clear = ila.const(0x0, 1)
pred_list = pred_map[pc]
for pred in pred_list:
pred_reg = self.model.getreg(pred + '_%d' % (index))
en_access_reg_next = ila.ite(pred_reg == ila.const(0x0, 1),
en_access_reg_next, en_access_reg)
if log:
self.model.set_next(
reg_name + '_en_%s_%d' % (suffix, pc),
ila.ite(
self.pc_list[index] == pc, en_access_reg_next,
ila.ite(self.log_clean, ila.const(0x0, 1),
en_access_reg)))
else:
self.model.set_next(
reg_name + '_en_%s_%d' % (suffix, pc),
ila.ite(
self.pc_list[index] == pc, en_access_reg_next,
ila.ite(self.check_clean, ila.const(0x0, 1),
en_access_reg)))
def generate_next_state(self, index):
instruction_book_obj = open('instruction_book', 'r')
instruction_book = instruction_book_obj.readlines()
current_pc = 0
next_state_finished = []
pc_target = {}
current_pc = 0
for program_line in program:
if len(program_line) < 2:
if len(program_line) == 0:
continue
if program_line[0][-1] == ':':
pc_target[program_line[0][:-1]] = current_pc
else:
current_pc += 4
current_pc = 0
for program_line in program:
if len(program_line) < 2:
continue
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
#opcode_length = int(opcode_split[-1][1:])
current_pc_in = current_pc
if opcode_name == 'ld':
current_pc += 4
if opcode_name == 'cvta':
dest_type = ptx_declaration[program_line[1]]
src_type = ptx_declaration[program_line[2]]
dest_length = int(dest_type[2:])
src_length = int(src_type[2:])
dest = self.model.getreg(program_line[1] + '_%d' % (index))
src = self.model.getreg(program_line[2] + '_%d' % (index))
if dest_length > src_length:
src = ila.sign_extend(src, dest_length)
if dest_length < src_length:
src = src[(dest_length - 1):0]
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'mov':
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
dest = self.model.getreg(program_line[1] + '_%d' % (index))
src_str = program_line[2]
if src_str in ptx_declaration.keys():
src = self.model.getreg(src_str + '_%d' % (index))
src_type = ptx_declaration[program_line[2]]
src_length = int(src_type[2:])
if dest_length > src_length:
src = ila.sign_extend(src, dest_length)
if dest_length < src_length:
src = src[(dest_length - 1):0]
else:
src = ila.const(int(src_str), dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'add':
dest = self.model.getreg(program_line[1] + '_%d' % (index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d' % (index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d' % (index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1 = ila.const(int(src1_str), dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src0 + src1,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'shr':
dest = self.model.getreg(program_line[1] + '_%d' % (index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d' % (index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d' % (index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1 = ila.const(int(src1_str), dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
ila.ashr(src0, src1),
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'sub':
dest = self.model.getreg(program_line[1] + '_%d' % (index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d' % (index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d' % (index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1 = ila.const(int(src1_str), dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src0 - src1,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'mul':
dest = self.model.getreg(program_line[1] + '_%d' % (index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d' % (index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d' % (index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1 = ila.const(int(src1_str), dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src0 * src1,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'st':
current_pc += 4
if current_pc == current_pc_in: #Just to find if there's any instruction not in the instruction-book
print program_line
#a = self.model.reg('support', 32)
#self.model.set_next('support', self.model.getreg('s3') + self.model.getreg('s1'))
for reg_name in ptx_declaration.keys():
if reg_name not in next_state_finished:
reg = self.model.getreg(reg_name + '_%d' % (index))
self.model.set_next(reg_name + '_%d' % (index), reg)
self.pc_max = current_pc
def nextStateVALUFunction(self, threadNo):
m = self.model
self.vsource_reg0 = ila.ite(self.vsrc0 > 255, m.indexIntoVGPR(self.vsrc0 - m.const(0x100, VECTOR_SOURCE_BIT), threadNo), m.indexIntoSGPR(self.vsrc0))
self.vsource_reg1 = m.indexIntoVGPR(self.vsrc1)
self.vcc = m.indexIntoVGPR(0, 0, True)
self.vsource_reg0_ext = ila.ite(self.vsrc0 > 255, m.indexIntoVGPR(self.vsrc0 + m.const(0x1, VECTOR_SOURCE_BIT) - m.const(0x100, VECTOR_SOURCE_BIT), threadNo), m.indexIntoSGPR(self.vsrc0 + m.const(0x1,1)))
self.vsource_reg1_ext = m.indexIntoVGPR(self.vsrc1 + m.const(0x1, VECTOR_SOURCE_BIT - 1))
self.vdst_reg = m.indexIntoVGPR(self.vdst)
self.vdst_reg_ext = m.indexIntoVGPR(self.vdst + m.const(0x1, VECTOR_SOURCE_BIT - 1))
self.vsource_reg0_long = ila.concat(self.vsource_reg0_ext, self.vsource_reg0)
self.vsource_reg1_long = ila.concat(self.vsource_reg1_ext, self.vsource_reg1)
self.vdst_reg_long = ila.concat(self.vdst_reg, self.vdst_reg_ext)
self.nxt_dst_vop2 = ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_CNDMASK_B32, ila.ite(self.vcc[threadNo] != 0, self.vsource_reg1, slef.vsource_reg0),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_READLANE_B32, ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_WRITELANE_B32, , \
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_ADD_F32, self.vsource_reg0 + self.vsource_reg1,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_SUB_F32, self.vsource_reg0 - self.vsource_reg1,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_SUBREV_F32, self.vsource_reg1 - self.vsource_reg0 ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MAC_LEGACY_F32, self.vsource_reg0 * self.vsource_reg1 + self.vdst_reg,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MUL_LEGACY_F32, self.vsource_reg0 * self.vsource_reg1,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MUL_F32, self.vsource_reg0 * self.vsource_reg1.\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MUL_I32_I24, ila.sign_extend((self.vsource_reg0[23:0] * self.vsource_reg1[23:0])[30:0], VECTOR_REG_BITS),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MUL_HI_I32_I24, ila.sign_extend((self.vsource_reg0[23:0] * self.vsource_reg1[23:0])[47:32], VECTOR_REG_BITS),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MUL_U32_U24, (self.vsource_reg0[23:0] * self.vsource_reg1[23:0])[31:0],\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MUL_HI_U32_U24, ila.zero_extend((self.vsource_reg0[23:0] * self.vsource_reg1[23:0])[47:32], VECTOR_REG_BITS),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MIN_LEGACY_F32, ila.ite(self.vsource_reg0 < self.vsource_reg1, self.vsource_reg0, self.vsource_reg1),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MAX_LEGACY_F32, ila.ite(self.vsource_reg0 >= self.vsource_reg1, self.vsource_reg0, self.vsource_reg1),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MIN_F32, ila.ite(self.vsource_reg0 < self.vsource_reg1, self.vsource_reg0, self.vsource_reg1),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MAX_F32, ila.ite(self.vsource_reg0 > self.vsource_reg1, self.vsource_reg0, self.vsource_reg1),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MIN_I32, ila.ite(self.vsource_reg0 < self.vsource_reg1, self.vsource_reg0, self.vsource_reg1),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MAX_I32, ila.ite(self.vsource_reg0 > self.vsource_reg1, self.vsource_reg0, self.vsource_reg1),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MIN_U32, ila.ite(self.vsource_reg0 < self.vsource_reg1, self.vsource_reg0, self.vsource_reg1),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MAX_U32, ila.ite(self.vsource_reg0 > self.vsource_reg1, self.vsource_reg0, self.vsource_reg1),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_LSHR_B32, self.vsource_reg0 >> self.vsource_reg1[4:0],\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_LSHRREV_B32, self.vsource_reg1 >> self.vsource_reg0[4:0],\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_ASHR_I32, ila.ashr(self.vsource_reg0, self.vsource_reg1[4:0]),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_ASHRREV_I32, ila.ashr(self.vsource_reg1, self.vsource_reg0[4:0]),\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_LSHL_B32, self.vsource_reg0 << self.vsource_reg1[4:0],\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_LSHLREV_B32, self.vsource_reg1 << self.vsource_reg0[4:0],\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_AND_B32, self.vsource_reg0 & self.vsource_reg1,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_OR_B32, self.vsource_reg0 | self.vsource_reg1,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_XOR_B32, self.vsource_reg0 ^ self.vsource_reg1,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_BFM_B32, ((1 << self.vsource_reg0[4:0]) - 1) << self.vsource_reg1[4:0],\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MAC_F32, self.vsource_reg0 * self.vsource_reg1 + self.vdst_reg,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MADMK_F32, ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MADAK_F32, ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_BCNT_U32_B32, aux_count(self.vsource_reg0, False ,VECTOR_REG_BITS) + self.vsource_reg1,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MBCNT_LO_U32_B32, ,\ #TODO: ThreadMask
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_MBCNT_HI_U32_B32, ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_ADD_I32, self.vsource_reg0 + self.vsource_reg1 ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_SUB_I32, self.vsource_reg0 - self.vsource_reg1, \
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_SUBREV_I32, self.vsource_reg1 - self.vsource_reg1,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_ADDC_U32, self.vsource_reg0 + self.vsource_reg1 + self.vcc[threadNo],\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_SUBB_U32, self.vsource_reg0 - self.vsource_reg1 - self.vcc[threadNo],\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_SUBBREV_U32, self.vsource_reg1 - self.vsource_reg0 - self.VCC[threadNo],\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_LDEXP_F32, ,\#TODO:EXP
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_CVT_PKACCUM_U8_F32, ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_CVT_PKNORM_I16_F32, ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_CVT_PKNORM_U16_F32, ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_CVT_PKRTZ_F16_F32, ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_CVT_PK_U16_U32, ,\
ila.ite( self.opcode_VOP2 == Encoding.VOP2_V_CVT_PK_I16_I32, ,\
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
def aux_ff_bit_m(self, src_reg, bits, find_bit):
result = ila.sign_extend(m.const(0x11, 2), SCALAR_REG_BITS)
for i in range(bits)[::-1]:
result = ila.ite(result < 0, ila.ite(src_reg[i] == find_bit, m.const(i, SCALAR_REG_BITS), result), result)
return result
def generate_next_state(self, index):
dreg_index = self.dreg_index_list[index]
sreg0_index = self.sreg0_index_list[index]
sreg1_index = self.sreg1_index_list[index]
sreg2_index = self.sreg2_index_list[index]
pred_enable = self.pred_enable_list[index]
pred_index = self.pred_index_list[index]
mul_op = self.mul_op_list[index]
dst_long_flag = self.dst_long_list[index]
src0_long_flag = self.src0_long_list[index]
src1_long_flag = self.src1_long_list[index]
src2_long_flag = self.src2_long_list[index]
dreg_scalar_reg = self.get_scalar_reg(dreg_index)
dreg_long_scalar_reg = self.get_long_scalar_reg(dreg_index)
sreg0_scalar_reg = self.get_scalar_reg(sreg0_index)
sreg0_long_scalar_reg = self.get_long_scalar_reg(sreg0_index)
sreg1_scalar_reg = self.get_scalar_reg(sreg1_index)
sreg1_long_scalar_reg = self.get_long_scalar_reg(sreg1_index)
sreg2_scalar_reg = self.get_scalar_reg(sreg2_index)
sreg2_long_scalar_reg = self.get_long_scalar_reg(sreg2_index)
dreg = ila.ite(
dst_long_flag, dreg_long_scalar_reg,
ila.sign_extend(dst_scalar_reg, instruction_format.LONG_REG_BITS))
sreg0 = ila.ite(
src0_long_flag, sreg0_long_scalar_reg,
ila.sign_extend(sreg0_scalar_reg,
instruction_format.LONG_REG_BITS))
sreg1 = ila.ite(
sreg1_long_flag, sreg1_long_scalar_reg,
ila.sign_extend(sreg1_scalar_reg,
instruction_format.LONG_REG_BITS))
sreg2 = ila.ite(
sreg2_long_flag, sreg2_long_scalar_reg,
ila.sign_extend(sreg2_scalar_reg,
instruction_format.LONG_REG_BITS))
#Generate Ret Expression
mov_ret_long = sreg0
mov_ret = mov_ret_long[(instruction_format.REG_BITS - 1):0]
cvta_ret_long = sreg0
cvta_ret = sreg0[(instruction_format.REG_BITS - 1):0]
and_ret_long = sreg0 & sreg1
and_ret = and_result[(instruction_format.REG_BITS - 1):0]
shr_ret_long = ila.ashr(sreg0, sreg1)
shr_ret = shr_result[(instruction_format.REG_BITS - 1):0]
shl_result = sreg0 << sreg1
shl_ret = shl_result[(instruction_format.REG_BITS - 1):0]
add_result = sreg0 + sreg1
add_ret = add_result[(instruction_format.REG_BITS - 1):0]
sub_result = sreg0 - sreg1
sub_ret = sub_result[(instruction_format.REG_BITS - 1):0]
mul_wide_ret = sreg0 * sreg1
mul_lo_result = sreg0 * sreg1
mul_lo_ret = mul_lo_result[(instruction_format.REG_BITS - 1):0]
mad_wide_ret = sreg0 * sreg1 + sreg2
mad_lo_result = sreg0 * sreg1 + sreg2
mad_lo_ret = mad_lo_result[(instruction_format.REG_BITS - 1):0]
ne_ret = (sreg0 != sreg1)
gt_ret = (sreg0 > sreg1)
lt_ret = (sreg0 < sreg1)
le_ret = (sreg0 < sreg1) | (sreg0 == sreg1)
next_state_long = ila.ite(
self.is_mov_list[index], mov_ret_long,
ila.ite(
self.is_cvta_list[index], cvta_ret_long,
ila.ite(
self.is_and_list[index], and_ret_long,
ila.ite(
self.is_shr_list[index], shr_ret_long,
ila.ite(
self.is_shl_list[index], shl_ret_long,
ila.ite(
self.is_add_list[index], add_ret_long,
ila.ite(
self.is_sub_list[index], sub_ret_long,
ila.ite(
self.is_mul_list[index], mul_wide_ret,
ila.ite(self.is_mad_list[index],
mad_wide_ret,
dreg_long_scalar_reg)))))))))
next_state = ila.ite(
self.is_mov_list[index], mov_ret,
ila.ite(
self.is_cvta_list[index], cvta_ret,
ila.ite(
self.is_and_list[index], and_ret,
ila.ite(
self.is_shr_list[index], shr_ret,
ila.ite(
self.is_shl_list[index], shl_ret,
ila.ite(
self.is_add_list[index], add_ret,
ila.ite(
self.is_sub_list[index], sub_ret,
ila.ite(
self.is_mul_list[index], mul_wide_ret,
ila.ite(self.is_mad_list[index],
mad_wide_ret,
dreg_scalar_reg)))))))))
#TODO: scalar_registers, and long_scalar_registers should be 2-D
#ptx_reg_name_list add, pred_reg_next
for i in range(len(self.scalar_registers[index])):
this_reg = self.model.getreg(ptx_sreg_name_list[i] + '_%d' %
(index))
self.model.set_next(
ptx_reg_name_list[i] + '_%d' % (index),
ila.ite(dst_long_flag, this_reg,
ila.ite(dreg_index == i, next_state, this_reg)))
for i in range(len(self.long_scalar_registers[index])):
this_reg = self.model.getreg(ptx_long_reg_name_list[i] + '_%d' %
(index))
self.model.set_next(
ptx_long_reg_name_list[i] + '_%d' % (index),
ila.ite(dst_long_flag,
ila.ite(dreg_index == i, next_state_long.this_reg),
this_reg))
def aux_dest(self, opcode, src_list, index):
dest = None
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
if opcode_name == 'mov':
dest = src_list[0]
if opcode_name == 'and':
dest = src_list[0] & src_list[1]
if opcode_name == 'cvta':
dest = src_list[0]
if opcode_name == 'shr':
dest = ila.ashr(src_list[0], src_list[1])
if opcode_name == 'shl':
dest = src_list[0] << src_list[1]
if opcode_name == 'add':
dest = src_list[0] + src_list[1]
if opcode_name == 'sub':
dest = src_list[0] - src_list[1]
if opcode_name == 'mul':
opcode_width = opcode_split[1]
op_len = int(opcode_split[2][1:])
if opcode_width == 'wide':
src0 = ila.sign_extend(src_list[0], op_len * 2)
src1 = ila.sign_extend(src_list[1], op_len * 2)
dest = src0 * src1
elif opcode_width == 'lo':
src0 = ila.sign_extend(src_list[0], op_len * 2)
src1 = ila.sign_extend(src_list[1], op_len * 2)
dest_long = src0 * src1
dest = dest_long[(op_len - 1):0]
if opcode_name == 'mad':
opcode_width = opcode_split[1]
op_len = int(opcode_split[2][1:])
if opcode_width == 'lo':
src0 = ila.sign_extend(src_list[0], op_len * 2)
src1 = ila.sign_extend(src_list[1], op_len * 2)
src2 = ila.sign_extend(src_list[2], op_len * 2)
dest_long = src0 * src1 + src2
dest = dest_long[(op_len - 1):0]
if opcode_name == 'setp':
opcode_cmp = opcode_split[1]
if opcode_cmp == 'ne':
dest = ila.ite(src_list[0] != src_list[1], self.pred_one,
self.pred_zero)
if opcode_cmp == 'gt':
dest = ila.ite(src_list[0] > src_list[1], self.pred_one,
self.pred_zero)
if opcode_cmp == 'lt':
dest = ila.ite(src_list[0] < src_list[1], self.pred_one,
self.pred_zero)
if opcode_cmp == 'le':
dest = ila.ite(
(src_list[0] < src_list[1]) | (src_list[0] == src_list[1]),
self.pred_one, self.pred_zero)
if opcode_name == 'bar':
if opcode_split[1] == 'arrive':
self.bar_arrive_inst[index] = self.bar_arrive_inst[index] | (
self.pc_list[index] == self.current_pc)
if self.current_pc not in self.bar_arrive_list:
self.bar_arrive_list.append(self.current_pc)
elif opcode_split[1] == 'sync':
self.bar_sync_inst[index] = self.bar_sync_inst[index] | (
self.pc_list[index] == self.current_pc)
if self.current_pc not in self.bar_sync_list:
self.bar_sync_list.append(self.current_pc)
else:
self.bar_aux_inst[index] = self.bar_aux_inst[index] | (
self.pc_list[index] == self.current_pc)
if self.current_pc not in self.bar_aux_list:
self.bar_aux_list.append(self.current_pc)
#TODO: pc_next when bar
return dest
def create_data_race_element(self, log):
if log == True:
index = 0
bar_pass = ((self.is_bar_list[0]) & (self.is_bar_list[1]))
mem_lsg_type = self.fetch_inst_list[index][(
instruction_format.MEM_LSG_TOP -
1):instruction_format.MEM_LSG_BOT]
is_log_mem_access = (self.is_ld_list[index]) | (
self.is_st_list[index])
src0_long_flag = self.src0_long_list[index]
sreg0_index = self.sreg0_index_list[index]
sreg0_scalar_reg = self.get_scalar_reg(sreg0_index)
sreg0_long_scalar_reg = self.get_long_scalar_reg(sreg0_index)
sreg0 = ila.ite(
src0_long_flag,
sreg0_long_scalar_reg[(instruction_format.DMEM_BITS - 1):0],
sreg0_scalar_reg)
imm_addr = ila.sign_extend(self.imm_list[index],
instruction_format.DMEM_BITS)
mem_address = sreg0 + imm_addr
#Assume ld/st 32bits address
log_register_next = ila.ite(
is_log_mem_access,
ila.ite(self.arb_list[index] == 1, mem_address,
self.log_register), self.log_register)
en_log_register_next = ila.ite(
bar_pass, ila.bool(False),
ila.ite(
is_log_mem_access,
ila.ite(self.arb_list[index] == 1, ila.bool(True),
en_log_register), en_log_register))
lsg_log_register_next = ila.ite(
is_log_mem_access,
ila.ite(self.arb_list[index] == 1, mem_lsg_type,
lsg_log_register), lsg_log_register)
self.model.set_next('log_regiseter', log_register_next)
self.model.set_next('en_log_register', en_log_register_next)
self.model.set_next('lsg_log_register', lsg_log_register_next)
else:
index = 1
bar_pass = ((self.is_bar_list[0]) & (self.is_bar_list[1]))
mem_lsg_type = self.fetch_inst_list[index][(
instruction_format.MEM_LSG_TOP -
1):instruction_format.MEM_LSG_BOT]
is_check_mem_access = (self.is_st_list[index])
src0_long_flag = self.src0_long_list[index]
sreg0_index = self.sreg0_index_list[index]
sreg0_scalar_reg = self.get_scalar_reg(sreg0_index)
sreg0_long_scalar_reg = self.get_long_scalar_reg(sreg0_index)
sreg0 = ila.ite(
src0_long_flag,
sreg0_long_scalar_reg[(instruction_format.DMEM_BITS - 1):0],
sreg0_scalar_reg)
imm_addr = ila.sign_extend(self.imm_list[index],
instruction_format.DMEM_BITS)
mem_address = sreg0 + imm_addr
#Assume ld/st 32bits address
check_register_next = ila.ite(
is_check_mem_access,
ila.ite(self.arb_list[index] == 1, mem_address,
self.check_register), self.check_register)
en_check_register_next = ila.ite(
bar_pass, ila.bool(False),
ila.ite(
is_check_mem_access,
ila.ite(self.arb_list[index] == 1, ila.bool(True),
en_check_register), en_check_register))
lsg_check_register_next = ila.ite(
is_check_mem_access,
ila.ite(self.arb_list[index] == 1, mem_lsg_type,
lsg_check_register), lsg_check_register)
self.model.set_next('check_register', check_register_next)
self.model.set_next('en_check_register', en_check_register_next)
self.model.set_next('lsg_check_register'.lsg_check_register_next)
def generate_next_state(self, index):
instruction_book_obj = open('instruction_book', 'r')
instruction_book = instruction_book_obj.readlines()
current_pc = 0
next_state_finished = []
pc_target = {}
current_pc = 0
for program_line in program:
if len(program_line) < 2:
if len(program_line) == 0:
continue
if program_line[0][-1] == ':':
pc_target[program_line[0][:-1]] = current_pc
else:
current_pc += 4
print pc_target
current_pc = 0
for program_line in program:
if len(program_line) < 2:
continue
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
#opcode_length = int(opcode_split[-1][1:])
current_pc_in = current_pc
if opcode_name == 'setp':
opcode_cmp = opcode_split[1]
dest_str = program_line[1]
src0_str = program_line[2]
src1_str = program_line[3]
dest_pred = self.model.getreg(dest_str + '_%d' % (index))
(src0, src0_length) = self.aux_imm(src0_str, index)
(src1, src1_length) = self.aux_imm(src1_str, index)
if src0_length > src1_length:
src1 = ila.sign_extend(src1, src0_length)
if src1_length > src0_length:
src0 = ila.sign_extend(src0, src1_length)
if opcode_cmp == 'gt':
dest = ila.ite(src0 > src1, self.model.const(0x1, 1),
self.model.const(0x0, 1))
if opcode_cmp == 'lt':
dest = ila.ite(src0 < src1, self.model.const(0x1, 1),
self.model.const(0x0, 1))
if opcode_cmp == 'ne':
dest = ila.ite(src0 != src1, self.model.const(0x1, 1),
self.model.const(0x0, 1))
self.next_state_dict[dest_str + '_%d' % (index)] = ila.ite(
self.pc_list[index] == current_pc, dest,
self.next_state_dict[dest_str + '_%d' % (index)])
next_state_finished.append(dest_str)
current_pc += 4
if opcode_name == '@':
opcode_pred_name = program_line[1]
opcode_pred = self.model.getreg(opcode_pred_name + '_%d' %
(index))
opcode_jmp_dest = program_line[3]
opcode_jmp_target = pc_target[opcode_jmp_dest]
print opcode_jmp_target
pc_jmp = ila.ite(
opcode_pred == 1,
ila.const(opcode_jmp_target, instruction_format.PC_BITS),
self.pc_list[index] + 4)
self.pc_next_list[index] = ila.ite(
self.pc_list[index] == current_pc, pc_jmp,
self.pc_next_list[index])
current_pc += 4
if opcode_name == 'ld':
current_pc += 4
if opcode_name == 'cvta':
dest_type = ptx_declaration[program_line[1]]
src_type = ptx_declaration[program_line[2]]
dest_length = int(dest_type[2:])
src_length = int(src_type[2:])
dest = self.model.getreg(program_line[1] + '_%d' % (index))
src = self.model.getreg(program_line[2] + '_%d' % (index))
if dest_length > src_length:
src = ila.sign_extend(src, dest_length)
if dest_length < src_length:
src = src[(dest_length - 1):0]
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'mov':
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
dest = self.model.getreg(program_line[1] + '_%d' % (index))
src_str = program_line[2]
if src_str in ptx_declaration.keys():
src = self.model.getreg(src_str + '_%d' % (index))
src_type = ptx_declaration[program_line[2]]
src_length = int(src_type[2:])
if dest_length > src_length:
src = ila.sign_extend(src, dest_length)
if dest_length < src_length:
src = src[(dest_length - 1):0]
else:
src = ila.const(int(src_str), dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'shr':
dest = self.model.getreg(program_line[1] + '_%d' % (index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d' % (index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d' % (index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1 = ila.const(int(src1_str), dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
ila.ashr(src0, src1),
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'sub':
dest = self.model.getreg(program_line[1] + '_%d' % (index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d' % (index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d' % (index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1 = ila.const(int(src1_str), dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src0 - src1,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'and':
dest = self.model.getreg(program_line[1] + '_%d' % (index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d' % (index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d' % (index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1_int = int(src1_str)
if src1_int < 0:
src1_int = -src1_int
src1_int = (
1 <<
(instruction_format.REG_BITS - 1)) - src1_int + (
1 << (instruction_format.REG_BITS - 1))
src1 = ila.const(src1_int, dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src0 & src1,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'add':
dest = self.model.getreg(program_line[1] + '_%d' % (index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d' % (index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d' % (index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1 = ila.const(int(src1_str), dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src0 + src1,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'mul':
dest = self.model.getreg(program_line[1] + '_%d' % (index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d' % (index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d' % (index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1 = ila.const(int(src1_str), dest_length)
self.next_state_dict[program_line[1] + '_%d' %
(index)] = ila.ite(
self.pc_list[index] == current_pc,
src0 * src1,
self.next_state_dict[program_line[1] +
'_%d' % (index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'st':
current_pc += 4
if current_pc == current_pc_in: #Just to find if there's any instruction not in the instruction-book
print program_line
#a = self.model.reg('support', 32)
#self.model.set_next('support', self.model.getreg('s3') + self.model.getreg('s1'))
for reg_name in ptx_declaration.keys():
if reg_name not in next_state_finished:
reg = self.model.getreg(reg_name + '_%d' % (index))
self.model.set_next(reg_name + '_%d' % (index), reg)
self.pc_max = current_pc
def instructionFetch(self):
self.inst = ila.load(
self.mem,
ila.zero_extend(self.pc[31:3],
instruction_format.MEM_ADDRESS_BITS))
self.opcode = self.inst[(instruction_format.OPCODE_BIT_TOP -
1):instruction_format.OPCODE_BIT_BOT]
self.fetch_expr = self.inst
self.dest = self.inst[(instruction_format.DST_BIT_TOP -
1):instruction_format.DST_BIT_BOT]
self.src1 = self.inst[(instruction_format.SRC0_BIT_TOP -
1):instruction_format.SRC0_BIT_BOT]
self.src2 = self.inst[(instruction_format.SRC1_BIT_TOP -
1):instruction_format.SRC1_BIT_BOT]
self.src3 = self.inst[(instruction_format.SRC2_BIT_TOP -
1):instruction_format.SRC2_BIT_BOT]
self.baseImm = ila.sign_extend(
self.inst[(instruction_format.BASE_BIT_TOP -
1):instruction_format.BASE_BIT_BOT],
instruction_format.PC_BITS)
#self.branchPred = self.dest
#(self.predReg, self.predReg_flag) = self.indexIntoReg(self.branchPred)
self.branchImm = ila.zero_extend(
self.inst[(instruction_format.IMM_BIT_TOP -
1):instruction_format.IMM_BIT_BOT],
instruction_format.PC_BITS)
self.ldImm = ila.zero_extend(
self.inst[(instruction_format.IMM_BIT_TOP -
1):instruction_format.IMM_BIT_BOT],
instruction_format.PC_BITS)
self.stImm = ila.zero_extend(
self.inst[(instruction_format.IMM_BIT_TOP -
1):instruction_format.IMM_BIT_BOT],
instruction_format.PC_BITS)
self.sreg1_flag = ila.ite((self.src1 >= self.scalar_register_num) &
(self.src1 < self.register_total_num),
self.long_scalar_register_flag,
self.scalar_register_flag)
self.sreg2_flag = ila.ite((self.src2 >= self.scalar_register_num) &
(self.src2 < self.register_total_num),
self.long_scalar_register_flag,
self.scalar_register_flag)
self.sreg3_flag = ila.ite((self.src3 >= self.scalar_register_num) &
(self.src3 < self.register_total_num),
self.long_scalar_register_flag,
self.scalar_register_flag)
self.sregdest_flag = ila.ite((self.dest >= self.scalar_register_num) &
(self.dest < self.register_total_num),
self.long_scalar_register_flag,
self.scalar_register_flag)
self.ssreg1 = self.indexIntoSReg(self.src1)
self.ssreg2 = self.indexIntoSReg(self.src2)
self.ssreg3 = self.indexIntoSReg(self.src3)
self.ssregdest = self.indexIntoSReg(self.dest)
self.lsreg1 = self.indexIntoLReg(self.src1)
self.lsreg2 = self.indexIntoLReg(self.src2)
self.lsreg3 = self.indexIntoLReg(self.src3)
self.lsregdest = self.indexIntoLReg(self.dest)
self.sreg1 = ila.ite(self.sreg1_flag, self.ssreg1,
self.lsreg1[instruction_format.REG_BITS - 1:0])
self.sreg2 = ila.ite(self.sreg2_flag, self.ssreg2,
self.lsreg2[instruction_format.REG_BITS - 1:0])
self.sreg3 = ila.ite(self.sreg3_flag, self.ssreg3,
self.lsreg3[instruction_format.REG_BITS - 1:0])
self.sregdest = ila.ite(
self.sregdest_flag, self.ssregdest,
self.lsregdest[instruction_format.REG_BITS - 1:0])
def nxtStateFunction(self):
######next state function for pc
m = self.model
self.pc_nxt_32 = self.pc + m.const(0x1, PC_REG_BITS)
self.pc_nxt_64 = self.pc + m.const(0x2, PC_REG_BITS)
self.source_reg0 = m.indexIntoSGPR(self.ssrc0)
self.source_reg1 = m.indexIntoSGPR(self.ssrc1)
self.scc = m.indexIntoSGPR(0, False, True)
self.exec = m.indexIntoSGPR(0, False, False, True)
self.source_reg0_ext = m.indexIntoSGPR(self.ssrc0 + m.const(0x1))
self.source_reg1_ext = m.indexIntoSGPR(self.ssrc1 + m.const(0x1))
self.dst_reg = m.indexIntoSGPR(self.sdstSOP2)
self.dst_reg_ext = m.indexIntoSGPR(self.sdstSOP2 + m.const(0x1))
self.source_reg0_long = ila.concat(self.source_reg0_ext, self.source_reg0)
self.source_reg1_long = ila.concat(self.source_reg1_ext, self.source_reg1)
self.dst_reg_long = ila.concat(self.dst_reg, self.dst_reg_ext)
self.source_reg2_bfe = self.source_reg1[20:16]
self.source_reg1_bfe = self.source_reg1[4:0]
self.source_reg2_bfe_long = self.source_reg1[22:16]
self.source_reg1_bfe_long = self.source_reg1[5:0]
self.nxt_dst_sop2 = ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_ABSDIFF_I32_OPCODE, \
ila.ite(self.source_reg0 > self.source_reg1, self.source_reg0 - self.source_reg1, self.source_reg1 - self.source_reg0), \
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_ADD_I32_OPCODE, self.source_reg0 + self.source_reg1,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_ADD_U32_OPCODE, self.source_reg0 + self.source_reg1,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_ADDC_U32_OPCODE, self.source_reg0 + self.source_reg1 + self.scc,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_AND_B32_OPCODE, self.source_reg0 & self.source_reg1,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_AND_B64_OPCODE, self.source_reg0_long & self.source_reg1_long,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_ANDN2_B32_OPCODE, self.source_reg0 & (~self.source_reg1),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_ANDN2_B64_OPCODE, self.source_reg0_long & (~self.source_reg1_long),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_ASHR_I32_OPCODE, ila.ashr(self.source_reg0, self.source_reg1[4:0]),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_ASHR_I64_OPCODE, ila.ashr(self.source_reg0_long, self.source_reg1_long[5:0]),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_BFE_I32_OPCODE, ila.ite(self.source_reg2_bfe == 0, m.const(0, SCALAR_REG_BITS), ila.ite((self.source_reg2_bfe + self.source_reg1_bfe) < 32, (self.source_reg0 << (SCALAR_REG_BITS - self.source_reg2_bfe - self.source_reg1_bfe)) >> (32 - self.source_reg2_bfe), source_reg0 >> source_reg1_bfe)),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_BFE_U32_OPCODE, ila.ite(self.source_reg2_bfe == 0, m.const(0, SCALAR_REG_BITS), ila.ite((self.source_reg2_bfe + self.source_reg1_bfe) < 32, (self.source_reg0 << (SCALAR_REG_BITS - self.source_reg2_bfe - self.source_reg1_bfe)) >> (32 - self.source_reg2_bfe), source_reg0 >> source_reg1_bfe)),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_BFE_I64_OPCODE, (self.source_reg0 >> self.source_reg1_bfe_long) & ((1 << self.source_reg2_bfe_long) - 1), \
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_BFE_U64_OPCODE, (self.source_reg0 >> self.source_reg1_bfe_long) & ((1 << self.source_reg2_bfe_long) - 1), \
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_BFM_B32_OPCODE, ((1 << self.source_reg0[4:0]) - 1) << self.source_reg1[4:0],\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_BFM_B64_OPCODE, ((1 << self.source_reg0_long[5:0]) - 1) << self.source_reg1_long[5:0],\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_CBRANCH_G_FORK_OPCODE, ,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_CSELECT_B32_OPCODE, ila.ite(self.scc, self.source_reg0, self.source_reg1),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_CSELECT_B64_OPCODE, ila.ite(self.scc, self.source_reg0_long, self.source_reg1_long),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_LSHL_B32_OPCODE, self.source_reg0 << self.source_reg1[4:0],\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_LSHL_B64_OPCODE, self.source_reg0_long << self.source_reg1_long[5:0],\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_LSHR_B32_OPCODE, self.source_reg0 >> self.source_reg0[4:0],\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_LSHR_B64_OPCODE, self.source_reg0_long >> self.source_reg1_long[5:0],\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_MAX_I32_OPCODE, ila.ite(self.source_reg0 > self.source_reg1, self.source_reg0, self.source_reg1),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_MAX_U32_OPCODE, ila.ite(self.source_reg0 > self.source_reg1, self.source_reg0, self.source_reg1),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_MIN_I32_OPCODE, ila.ite(self.source_reg0 < self.source_reg1, self.source_reg0, self.source_reg1),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_MIN_U32_OPCODE, ila.ite(self.source_reg0 < self.source_reg1, self.source_reg0, self.source_reg1),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_MUL_I32_OPCODE, self.source_reg0 * self.source_reg1 ,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_NAND_B32_OPCODE, ~(self.source_reg0 & self.source_reg1),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_NAND_B64_OPCODE, ~(self.source_reg0_long & self.source_reg1_long),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_NOR_B32_OPCODE, ~(self.source_reg0 | self.source_reg1),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_NOR_B64_OPCODE, ~(self.source_reg0_long | self.source_reg1_long),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_OR_B32_OPCODE, self.source_reg0 | self.source_reg1,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_OR_B64_OPCODE, self.source_reg0_long | self.source_reg1_long,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_ORN2_B32_OPCODE, self.source_reg0 | (~self.source_reg1),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_ORN2_B64_OPCODE, self.source_reg0_long | (~self.source_reg1_long),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_SUB_I32_OPCODE, self.source_reg0 - self.source_reg1 ,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_SUB_U32_OPCODE, self.source_reg0 - self.source_reg1,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_SUBB_U32_OPCODE, self.source_reg0 - self.source_reg1 - self.scc,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_XNOR_B32_OPCODE, ~(self.source_reg0 ^ self.source_reg1),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_XNOR_B64_OPCODE, ~(self.source_reg0_long ^ self.source_reg1_long),\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_XOR_B32_OPCODE, self.source_reg0 ^ self.source_reg1,\
ila.ite(self.opcode_SOP2 == Encoding.SOP2_S_XOR_B64_OPCODE, self.source_reg0_long ^ self.source_reg1_long),\
self.dst_reg\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
)\
self.nxt_dst_sop1 = ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_ABS_I32_OPCODE, ile.ite(self.source_reg0 > 0, self.source_reg0, -self.source_reg0),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_AND_SAVEEXEC_B64_OPCODE, self.exec,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_ANDN2_SAVEEXEC_B64_OPCODE, self.exec, \
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_BCNT0_I32_B32_OPCODE, aux_count(self.source_reg0, m.const(0x1, 1), m.const(SCALAR_REG_BITS)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_BCNT0_I32_B64_OPCODE, aux_count(self.source_reg0, m.const(0x1, 1), m.const(SCALAR_REG_BITS_LONG)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_BCNT1_I32_B32_OPCODE, aux_count(self.source_reg0, m.const(0x1, 0), m.const(SCALAR_REG_BITS)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_BCNT1_I32_B64_OPCODE, aux_count(self.source_reg0, m.const(0x1, 0), m.const(SCALAR_REG_BITS_LONG)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_BITSET0_B32_OPCODE, aux_bit_set_zero(self.dst_reg, self.source_reg0[4:0]),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_BITSET0_B64_OPCODE, aux_bit_set_zero(self.dst_reg_long, self.source_reg0_long[5:0]),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_BITSET1_B32_OPCODE, aux_bit_set_one(self.dst_reg, self.source_reg0[4:0]),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_BITSET1_B64_OPCODE, aux_bit_set_one(self.dst_reg_long, self.source_reg0_long[5:0]),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_BREV_B32_OPCODE, aux_bit_rev(self.source_reg0, SCALAR_REG_BITS),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_BREV_B64_OPCODE, aux_bit_rev(self.source_reg0_long, SCALAR_REG_BITS_LONG),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_CBRANCH_JOIN_OPCODE, #TODO
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_CMOV_B32_OPCODE, ila.ite(self.scc, self.source_reg0, ~(self.source_reg0 | self.dst_reg)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_CMOV_B64_OPCODE, ila.ite(self.scc, self.source_reg0_long, ~(self.source_reg0_long | self.dst_reg_long)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_FF0_I32_B32_OPCODE, aux_ff_bit(self.source_reg0, SCALAR_REG_BITS, m.const(0x0, 1)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_FF1_I32_B32_OPCODE, aux_ff_bit(self.source_reg0, SCALAR_REG_BITS, m.const(0x1, 1)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_FF0_I32_B64_OPCODE, aux_ff_bit(self.source_reg0_long, SCALAR_REG_BITS_LONG, m.const(0x0, 1)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_FF1_I32_B64_OPCODE, aux_ff_bit(self.source_reg0_long, SCALAR_REG_BITS_LONG, m.const(0x1, 1)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_FLBIT_I32_OPCODE, aux_ff_op_bit(self.source_reg0, SCALAR_REG_BITS),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_FLBIT_I32_I64_OPCODE, aux_ff_op_bit(self.source_reg0_long, SCALAR_REG_BITS_LONG),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_FLBIT_I32_B32_OPCODE, aux_ff_bit_m(self.source_reg0, SCALAR_REG_BITS, m.const(0x1, 1)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_FLBIT_I32_B64_OPCODE, aux_ff_bit_m(self.source_reg0_long, SCALAR_REG_BITS_LONG, m.const(0x1, 1)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_GETPC_B64_OPCODE, self.pc + m.const(0x4, SCALAR_REG_BITS_LONG) ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_MOV_B32_OPCODE, self.source_reg0,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_MOV_B64_OPCODE, self.source_reg0_long,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_MOVRELD_B32_OPCODE, #TODO ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_MOVRELD_B64_OPCODE, #TODO ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_MOVRELS_B32_OPCODE, #TODO ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_MOVRELS_B64_OPCODE, #TODO ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_NAND_SAVEEXEC_B64_OPCODE, self.exec, \
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_NOR_SAVEEXEC_B64_OPCODE, self.exec,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_NOT_B32_OPCODE, ~(self.source_reg0),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_NOT_B64_OPCODE, ~(self.source_reg0_long),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_OR_SAVEEXEC_B64_OPCODE, self.exec,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_ORN2_SAVEEXEC_B64_OPCODE, self.exec ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_QUADMASK_B32_OPCODE, ila.zero_extend(aux_quadmask(self.source_reg0, SCALAR_REG_BITS)) ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_QUADMASK_B64_OPCODE, ila.zero_extend(aux_quadmask(self.source_reg0_long)),\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_RFE_B64_OPCODE, ila.source_reg0_long,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_WQM_B32_OPCODE, ila.zero_extend(aux_quadmask(self.source_reg0, SCALAR_REG_BITS)) ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_WQM_B64_OPCODE, ila.zero_extend(aux_quadmask(self.source_reg0, SCALAR_REG_BITS)) ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_SEXT_I32_I8_OPCODE, ila.sign_extend(self.source_reg0[7:0]) ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_SEXT_I32_I16_OPCODE, ila.sign_extend(self.source_reg0[15:0]) ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_SWAPPC_B64_OPCODE, self.pc + m.const(0x4, SCALAR_REG_BITS_LONG) ,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_MOV_FED_B32_OPCODE, self.source_reg0,\
ila.ite(self,opcode_SOP1 == Encoding.SOP1_S_XOR_SAVEEXEC_B64_OPCODE, self.exec,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_XNOR_SAVEEXEC_B64_OPCODE, self.exec,\
ila.ite(self.opcode_SOP1 == Encoding.SOP1_S_SETPC_B64_OPCODE, self.dst_reg,\
self.dst_reg
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
self.nxt_dst_sopk = ila.ite( self.opcode_SOPK == Encoding.SOPK_S_MOVK_I32_OPCODE, ila.sign_extend(self.simm, SCALAR_REG_BITS),\
ila.ite( self.opcode_SOPK == Encoding.SOPK_S_CMOVK_I32_OPCODE, ila.ite(self.scc != m.const(0x1, 1), ila.sign_extend(self.simm, SCALAR_REG_BITS, self.dst_reg)),\
ila.ite( self.opcode_SOPK == Encoding.SOPK_S_ADDK_I32_OPCODE, self.dst_reg + sign_extend(self.simm, SCALAR_REG_BITS),\
ila.ite( self.opcode_SOPK == Encoding.SOPK_S_MULK_I32_OPCODE, self.dst_reg * sign_extend(self.simm, SCALAR_REG_BITS),\
)
)
)
)
def buildTemplate():
aes = ila.Abstraction('aesr')
def _debug_print(dvar):
aes.set_next('debug', Lto32(dvar))
byte0 = ila.const(0, 8)
key0 = aes.reg('in_key0', 32)
key1 = aes.reg('in_key1', 32)
key2 = aes.reg('in_key2', 32)
key3 = aes.reg('in_key3', 32)
state0 = aes.reg('state0', 32)
state1 = aes.reg('state1', 32)
state2 = aes.reg('state2', 32)
state3 = aes.reg('state3', 32)
debug = aes.reg('debug', 32)
table0 = aes.mem('table', 10, 8)
rcon = aes.reg('rcon', 8)
i = aes.reg('i', 4)
aes.set_init('rcon', ila.const(1, 8))
aes.set_init('i', ila.const(1, 4))
# round 1
# but not the last one
tab = fulltable(table0)
[k0, k1, k2, k3] = [key0, key1, key2, key3]
stateL = [state0, state1, state2, state3]
stateL[0] = ila.ite(i == 1, stateL[0] ^ k0, stateL[0])
stateL[1] = ila.ite(i == 1, stateL[1] ^ k1, stateL[1])
stateL[2] = ila.ite(i == 1, stateL[2] ^ k2, stateL[2])
stateL[3] = ila.ite(i == 1, stateL[3] ^ k3, stateL[3])
k0 = _32toL(key0)
k1 = _32toL(key1)
k2 = _32toL(key2)
k3 = _32toL(key3)
for idx in range(4):
stateL[idx] = _32toL(stateL[idx])
tempL = k3
tempL = rot_down_8(tempL)
sub_byte(tempL, tab)
tempL = xor(tempL, [rcon, byte0, byte0, byte0])
j = ila.sign_extend(rcon, 32)
j = j << 1
j = j ^ ((j >> 8) & ila.const(0x1b, 32))
rcon = j[7:0] # set next ?
k0 = xor(k0, tempL)
k1 = xor(k1, k0)
k2 = xor(k2, k1)
k3 = xor(k3, k2)
z0 = k0[:]
z1 = k1[:]
z2 = k2[:]
z3 = k3[:]
bList = stateL[0] # this is a list
pListWord = table_lookup(bList, tab, byte0)
_debug_print(pListWord[0])
rot(pListWord)
z0 = xor(z0, pListWord[0])
z3 = xor(z3, pListWord[1])
z2 = xor(z2, pListWord[2])
z1 = xor(z1, pListWord[3])
bList = stateL[1]
pListWord = table_lookup(bList, tab, byte0)
rot(pListWord)
z1 = xor(z1, pListWord[0])
z0 = xor(z0, pListWord[1])
z3 = xor(z3, pListWord[2])
z2 = xor(z2, pListWord[3])
bList = stateL[2]
pListWord = table_lookup(bList, tab, byte0)
rot(pListWord)
z2 = xor(z2, pListWord[0])
z1 = xor(z1, pListWord[1])
z0 = xor(z0, pListWord[2])
z3 = xor(z3, pListWord[3])
bList = stateL[3]
pListWord = table_lookup(bList, tab, byte0)
rot(pListWord)
stateL[0] = xor(z0, pListWord[3])
stateL[1] = xor(z1, pListWord[2])
stateL[2] = xor(z2, pListWord[1])
stateL[3] = xor(z3, pListWord[0])
stateL[0] = Lto32(stateL[0])
stateL[1] = Lto32(stateL[1])
stateL[2] = Lto32(stateL[2])
stateL[3] = Lto32(stateL[3])
k0 = Lto32(k0)
k1 = Lto32(k1)
k2 = Lto32(k2)
k3 = Lto32(k3)
# set next to stateList
aes.set_next('state0', stateL[0])
aes.set_next('state1', stateL[1])
aes.set_next('state2', stateL[2])
aes.set_next('state3', stateL[3])
aes.set_next('i', i + 1)
aes.set_next('rcon', rcon)
aes.set_next('in_key0', k0)
aes.set_next('in_key1', k1)
aes.set_next('in_key2', k2)
aes.set_next('in_key3', k3)
aes.set_next('debug', debug)
aes.set_next('table', table0)
return aes
def aux_ff_op_bit(self, src_reg, bits):
result = ila.sign_extend(m.const(0x11, 2), SCALAR_REG_BITS)
for i in range(bits - 1)[::-1]:
result = ila.ite(result < 0, ila.ite(src_reg[bits - 1] != src_reg[i], m.const(i, SCALAR_REG_BITS_LONG), result), result)
return result
def synthesize(state, enable_ps):
uc = uc8051()
# create nicknames
pc, iram, sp = uc.pc, uc.iram, uc.sp
op0, op1, op2 = uc.op0, uc.op1, uc.op2
acc, b, dptr = uc.acc, uc.b, uc.dptr
psw = uc.psw
rx = uc.rx
rom = uc.rom
model = uc.model
model.enable_parameterized_synthesis = enable_ps
bv = model.const
# fetch and decode.
model.fetch_expr = uc.op0 # s/hand for uc.rom[uc.pc]
model.decode_exprs = [uc.op0 == i for i in xrange(0x0, 0x100)]
########################### PC ##############################################
def cjmp(name, cond):
pc_taken = ila.choice(name + '_taken', pc_rel1, pc_rel2)
pc_seq = ila.choice(name + '_seq', pc + 2, pc + 3)
return ila.ite(cond, pc_taken, pc_seq)
def jmppolarity(name):
return ila.inrange(name, bv(0, 1), bv(1, 1))
# ajmp/acall
pc_ajmp_pg1 = (pc + 2)[15:11]
pc_ajmp_pg2 = ila.inrange('ajmp_page', bv(0x0, 3), bv(0x7, 3))
pc_ajmp_pg = ila.concat(pc_ajmp_pg1, pc_ajmp_pg2)
pc_ajmp = ila.concat(pc_ajmp_pg, op1)
# lcall/ljmp
pc_ljmp = ila.choice('ljmp', [ila.concat(op2, op1), ila.concat(op1, op2)])
# ret.
pc_ret = ila.choice('pc_ret', [
ila.concat(iram[sp - 1], iram[sp]),
ila.concat(iram[sp], iram[sp - 1]),
ila.concat(iram[sp], iram[sp + 1]),
ila.concat(iram[sp + 1], iram[sp])
])
# relative to pc
pc_rel1 = ila.choice('pc_rel1_base', [pc, pc + 1, pc + 2, pc + 3
]) + ila.sign_extend(op1, 16)
pc_rel2 = ila.choice('pc_rel2_base', [pc, pc + 1, pc + 2, pc + 3
]) + ila.sign_extend(op2, 16)
# sjmp
pc_sjmp = ila.choice('sjmp', pc_rel1, pc_rel2)
# jb
jb_bitaddr = ila.choice('jb_bitaddr', [op1, op2])
jb_bit = uc.readBit(jb_bitaddr)
jx_polarity = jmppolarity('jx_polarity')
pc_jb = cjmp('pc_jb', jb_bit == jx_polarity)
# jc
pc_jc = cjmp('pc_jc', uc.cy == jx_polarity)
# jz
acc_zero = acc == 0
acc_nonzero = acc != 0
jz_test = ila.choice('jz_test_polarity', acc_zero, acc_nonzero)
pc_jz = cjmp('pc_jz', jz_test)
# jmp
pc_jmp = dptr + ila.zero_extend(acc, 16)
# cjne
cjne_src1 = ila.choice('cjne_src1', [acc, iram[rx[0]], iram[rx[1]]] + rx)
cjne_src2 = ila.choice(
'cjne_src2',
[op1, op2,
uc.readDirect(ila.choice('cjne_iram_addr', [op1, op2]))])
cjne_taken = cjne_src1 != cjne_src2
pc_cjne = cjmp('pc_cjne', cjne_taken)
# djnz
djnz_src = ila.choice(
'djnz_src',
[uc.readDirect(ila.choice('djnz_iram_src', [op1, op2]))] + rx)
djnz_taken = djnz_src != 1
pc_djnz = cjmp('pc_djnz', djnz_taken)
pc_choices = [
pc + 1, pc + 2, pc + 3, pc_ajmp, pc_ljmp, pc_ret, pc_sjmp, pc_jb,
pc_jc, pc_jz, pc_jmp, pc_cjne, pc_djnz
]
model.set_next('PC', ila.choice('pc', pc_choices))
########################### ACC ##############################################
# various sources for ALU ops.
acc_src2_dir_addr = ila.choice('acc_src2_dir_addr', [op1, op2])
acc_src2_dir = ila.choice('acc_src2_dir',
[uc.readDirect(acc_src2_dir_addr)] + rx)
acc_src2_indir_addr = ila.choice('acc_src2_indir_addr', [rx[0], rx[1]])
acc_src2_indir = iram[acc_src2_indir_addr]
src2_imm = ila.choice('src2_imm', [op1, op2])
acc_src2 = ila.choice('acc_src2', [acc_src2_dir, acc_src2_indir, src2_imm])
acc_rom_offset = ila.choice('acc_rom_offset',
[dptr, pc + 1, pc + 2, pc + 3])
# the decimal adjust instruction. this is a bit of mess.
# first, deal with the lower nibble
acc_add_6 = (uc.ac == 1) | (acc[3:0] > 9)
acc_ext9 = ila.zero_extend(acc, 9)
acc_da_stage1 = ila.ite(acc_add_6, acc_ext9 + 6, acc_ext9)
acc_da_cy1 = acc_da_stage1[8:8]
# and then the upper nibble
acc_add_60 = ((acc_da_cy1 | uc.cy) == 1) | (acc_da_stage1[7:4] > 9)
acc_da_stage2 = ila.ite(acc_add_60, acc_da_stage1 + 0x60, acc_da_stage1)
acc_da = acc_da_stage2[7:0]
# instructions which modify the accumulator.
acc_rr = ila.rrotate(acc, 1)
acc_rrc = ila.rrotate(ila.concat(acc, uc.cy), 1)[8:1]
acc_rl = ila.lrotate(acc, 1)
acc_rlc = ila.lrotate(ila.concat(uc.cy, acc), 1)[7:0]
acc_inc = acc + 1
acc_dec = acc - 1
acc_add = acc + acc_src2
acc_addc = acc + acc_src2 + ila.zero_extend(uc.cy, 8)
acc_orl = acc | acc_src2
acc_anl = acc & acc_src2
acc_xrl = acc ^ acc_src2
acc_subb = acc - acc_src2 + ila.sign_extend(uc.cy, 8)
acc_mov = acc_src2
acc_cpl = ~acc
acc_clr = bv(0, 8)
acc_rom = rom[ila.zero_extend(acc, 16) + acc_rom_offset]
acc_swap = ila.concat(acc[3:0], acc[7:4])
# div.
acc_div = ila.ite(b == 0, bv(0xff, 8), acc / b)
b_div = ila.ite(b == 0, acc, acc % b)
# mul
mul_result = ila.zero_extend(acc, 16) * ila.zero_extend(b, 16)
acc_mul = mul_result[7:0]
b_mul = mul_result[15:8]
# xchg - dir
xchg_src2_dir_addr = ila.choice('xchg_src2_dir_addr',
[op1, op2] + uc.rxaddr)
xchg_src2_dir = uc.readDirect(xchg_src2_dir_addr)
acc_xchg_dir = xchg_src2_dir
# xchg - indir
xchg_src2_indir_addr = ila.choice('xchg_src2_indir_addr', [rx[0], rx[1]])
xchg_src2_full_indir = iram[xchg_src2_indir_addr]
xchg_src2_half_indir = ila.concat(acc[7:4], xchg_src2_full_indir[3:0])
xchg_src2_indir = ila.choice('xchg_src2_indir',
[xchg_src2_full_indir, xchg_src2_half_indir])
acc_xchg_indir = xchg_src2_indir
# final acc value.
acc_next = ila.choice('acc_r_next', [
acc_rr, acc_rl, acc_rrc, acc_rlc, acc_inc, acc_dec, acc_add, acc_addc,
acc_orl, acc_anl, acc_xrl, acc_mov, acc_rom, acc_clr, acc_subb,
acc_swap, acc_cpl, acc, acc_div, acc_mul, acc_da, acc_xchg_dir,
acc_xchg_indir, uc.xram_data_in
])
model.set_next('ACC', acc_next)
########################### IRAM ##############################################
# instructions where the result is a direct iram address
dir_src1_addr = ila.choice('dir_src1_addr', [op1, op2] + uc.rxaddr)
dir_src1 = uc.readDirect(dir_src1_addr)
dir_src2_iram_addr = ila.choice('dir_src2_iram_addr',
[op1, op2] + uc.rxaddr)
dir_src2_iram = uc.readDirect(dir_src2_iram_addr)
dir_src2_indir_addr = ila.choice('dir_src2_indir_addr', [rx[0], rx[1]])
dir_src2_indir = iram[dir_src2_indir_addr]
dir_src2 = ila.choice('dir_src2',
[op1, op2, acc, dir_src2_iram, dir_src2_indir])
dir_inc = dir_src1 + 1
dir_dec = dir_src1 - 1
dir_orl = dir_src1 | dir_src2
dir_anl = dir_src1 & dir_src2
dir_xrl = dir_src1 ^ dir_src2
dir_mov = dir_src2
dir_result = ila.choice(
'dir_result', [dir_inc, dir_dec, dir_orl, dir_anl, dir_xrl, dir_mov])
dir_addrs = [dir_src1_addr]
dir_datas = [dir_result]
# write a bit.
bit_src1_addr = ila.choice('bit_src1_addr', [op1, op2])
bit_src1 = uc.readBit(bit_src1_addr)
wrbit_data = ila.choice(
'wrbit_data',
[uc.cy, ~uc.cy, bit_src1, ~bit_src1,
bv(0, 1), bv(1, 1)])
r_bit = uc.writeBit(bit_src1_addr, wrbit_data)
# some instructions write their result to the carry flag; which is also the first operand.
cy_orl = uc.cy | bit_src1
cy_orlc = uc.cy | ~bit_src1
cy_anl = uc.cy & bit_src1
cy_anlc = uc.cy & ~bit_src1
cy_mov = bit_src1
cy_cpl_bit = ~bit_src1
cy_cpl_c = ~uc.cy
bit_cnst1 = bv(1, 1)
bit_cnst0 = bv(0, 1)
bit_cy = ila.choice('bit_cy', [
cy_orl, cy_anl, cy_orlc, cy_anlc, cy_cpl_c, cy_mov, cy_cpl_bit,
bit_cnst1, bit_cnst0
])
# instructions where the result is an indirect iram address.
src1_indir_addr = ila.choice('src1_indir_addr', [rx[0], rx[1]])
src1_indir = iram[src1_indir_addr]
src2_indir_dir_addr = ila.choice('src2_indir_dir_addr', [op1, op2])
src2_indir_dir = uc.readDirect(src2_indir_dir_addr)
src2_indir = ila.choice('src2_indir', [op1, op2, acc, src2_indir_dir])
src1_indir_inc = src1_indir + 1
src1_indir_dec = src1_indir - 1
src1_indir_mov = src2_indir
src1_indir_result = ila.choice(
'src1_indir_result', [src1_indir_inc, src1_indir_dec, src1_indir_mov])
indir_addrs = [src1_indir_addr] # indirect write addr
indir_datas = [src1_indir_result] # and data.
# calls
pc_topush = ila.choice('pc_topush', [pc + 1, pc + 2, pc + 3])
pc_topush_lo = pc_topush[7:0]
pc_topush_hi = pc_topush[15:8]
pc_topush_0 = ila.choice('pc_topush_endianess',
[pc_topush_lo, pc_topush_hi])
pc_topush_1 = ila.choice('pc_topush_endianess',
[pc_topush_hi, pc_topush_lo])
pc_push_addr = ila.choice('pc_push_addr', [sp, sp + 1])
iram_call = ila.store(ila.store(iram, pc_push_addr, pc_topush_0),
pc_push_addr + 1, pc_topush_1)
# push or pop instructions.
stk_iram_addr = ila.choice('stk_iram_addr', [sp, sp + 1, sp - 1])
stk_src_dir_addr = ila.choice('stk_src_dir_addr', [op1, op2])
stk_src_dir = uc.readDirect(stk_src_dir_addr)
stk_src = ila.choice('stk_src', [stk_src_dir, acc])
sp_pushpop = ila.choice('sp_pushpop', sp + 1, sp - 1)
indir_addrs.append(stk_iram_addr)
indir_datas.append(stk_src)
stk_data = ila.choice('stk_data', [iram[sp], iram[sp + 1], iram[sp - 1]])
dir_addrs.append(stk_src_dir_addr)
dir_datas.append(stk_data)
r_pop = uc.writeDirect(stk_src_dir_addr, stk_data)
sp_pop = ila.ite(stk_src_dir_addr == bv(0x81, 8), r_pop.sp, sp_pushpop)
# exchanges; part of this implemented above in acc section.
dir_addrs.append(xchg_src2_dir_addr)
dir_datas.append(acc)
xchg_src1_half_indir = ila.concat(xchg_src2_full_indir[7:4], acc[3:0])
xchg_src1_indir = ila.choice('xchg_src1', [xchg_src1_half_indir, acc])
indir_addrs.append(xchg_src2_indir_addr)
indir_datas.append(xchg_src1_indir)
# final indirect writes.
iram_indir = ila.store(iram, ila.choice('iram_indir', indir_addrs),
ila.choice('iram_indir', indir_datas))
# final direct writes.
assert len(dir_addrs) == len(dir_datas)
r_dir = uc.writeDirect(ila.choice('iram_dir', dir_addrs),
ila.choice('iram_dir', dir_datas))
# set the next iram.
iram_next = ila.choice(
'iram_result', [iram, iram_indir, iram_call, r_dir.iram, r_bit.iram])
model.set_next('IRAM', iram_next)
########################### PSW ##############################################
cjne_cy = ila.ite(cjne_src1 < cjne_src2, bv(1, 1), bv(0, 1))
# muldiv
div_ov = ila.ite(b == 0, bv(1, 1), bv(0, 1))
mul_ov = ila.ite(b_mul != 0, bv(1, 1), bv(0, 1))
# da
acc_da_cy2 = acc_da_stage2[8:8]
acc_da_cy = acc_da_cy2 | acc_da_cy1 | uc.cy
# alu
alu_cy_in = ila.choice('alu_cy_in', [uc.cy, bv(0, 1)])
alu_cy_5b = ila.choice(
'alu_cy_5b',
[ila.zero_extend(alu_cy_in, 5),
ila.sign_extend(alu_cy_in, 5)])
alu_src1_lo_5b = ila.zero_extend(acc[3:0], 5)
alu_src2_lo_5b = ila.zero_extend(acc_src2[3:0], 5)
alu_ac_add = (alu_src1_lo_5b + alu_src2_lo_5b + alu_cy_5b)[4:4]
alu_ac_sub = ila.ite(alu_src1_lo_5b < (alu_src2_lo_5b + alu_cy_5b),
bv(1, 1), bv(0, 1))
alu_ac = ila.choice('alu_ac', [alu_ac_add, alu_ac_sub])
alu_src1_sext = ila.sign_extend(acc, 9)
alu_src2_sext = ila.sign_extend(acc_src2, 9)
alu_src1_zext = ila.zero_extend(acc, 9)
alu_src2_zext = ila.zero_extend(acc_src2, 9)
alu_cy_9b_sext = ila.sign_extend(alu_cy_in, 9)
alu_cy_9b_zext = ila.zero_extend(alu_cy_in, 9)
alu_cy_9b = ila.choice('alu_cy_9b', [alu_cy_9b_zext, alu_cy_9b_sext])
alu_zext_9b_sum = alu_src1_zext + alu_src2_zext + alu_cy_9b
alu_cy_add = alu_zext_9b_sum[8:8]
alu_cy_sub1 = ila.ite(alu_src1_zext < (alu_src2_zext + alu_cy_9b),
bv(1, 1), bv(0, 1))
alu_cy_sub2 = ila.ite(acc < (acc_src2 + ila.zero_extend(uc.cy, 8)),
bv(1, 1), bv(0, 1))
alu_cy = ila.choice('alu_cy', [alu_cy_add, alu_cy_sub1, alu_cy_sub2])
alu_ov_9b_src1 = ila.choice('alu_ov_9b_src1',
[alu_src1_sext, alu_src1_zext])
alu_ov_9b_src2 = ila.choice('alu_ov_9b_src2',
[alu_src2_sext, alu_src2_zext])
alu_9b_add = alu_ov_9b_src1 + alu_ov_9b_src2 + alu_cy_9b
alu_9b_sub = alu_ov_9b_src1 - alu_ov_9b_src2 + alu_cy_9b
alu_9b_res = ila.choice('alu_9b_res', [alu_9b_add, alu_9b_sub])
alu_ov = ila.ite(alu_9b_res[8:8] != alu_9b_res[7:7], bv(1, 1), bv(0, 1))
acc_cy = ila.choice('acc_cy', [uc.cy, acc[0:0], acc[7:7], alu_cy])
acc_ac = ila.choice('acc_ac', [uc.ac, alu_ac])
acc_ov = ila.choice('acc_ov', [uc.ov, alu_ov])
psw_bit = ila.concat(bit_cy, psw[6:0])
psw_cjne = ila.concat(cjne_cy, psw[6:0])
psw_div = ila.concat(bv(0, 1),
ila.concat(psw[6:3], ila.concat(div_ov, psw[1:0])))
psw_mul = ila.concat(bv(0, 1),
ila.concat(psw[6:3], ila.concat(mul_ov, psw[1:0])))
psw_da = ila.concat(acc_da_cy, psw[6:0])
psw_acc = ila.concat(
acc_cy,
ila.concat(acc_ac, ila.concat(psw[5:3], ila.concat(acc_ov, psw[1:0]))))
psw_next = ila.choice('psw_next', [
r_dir.psw, r_bit.psw, psw_cjne, psw_bit, psw_div, psw_mul, psw_da,
psw_acc, psw
])
model.set_next('PSW', psw_next)
########################### SP ##############################################
sp_next = ila.choice('sp_next', [
sp + 2, sp + 1, sp - 1, sp - 2, sp, sp_pop, r_pop.sp, r_dir.sp,
r_bit.sp
])
model.set_next('SP', sp_next)
########################### DPTR ##############################################
mov_dptr = ila.choice(
'mov_dptr',
[ila.concat(op1, op2), ila.concat(op2, op1)])
inc_dptr = dptr + 1
dptr_n1 = ila.choice('next_dptr', [mov_dptr, inc_dptr, dptr])
dpl_n1 = dptr[7:0]
dph_n1 = dptr[15:8]
dpl_next = ila.choice('dpl_next', [dpl_n1, r_dir.dpl, r_bit.dpl, uc.dpl])
dph_next = ila.choice('dph_next', [dph_n1, r_dir.dph, r_bit.dph, uc.dph])
model.set_next('DPL', dpl_next)
model.set_next('DPH', dph_next)
########################### B #################################################
b_next = ila.choice('b_next', [b_mul, b_div, r_bit.b, r_dir.b, uc.b])
model.set_next('B', b_next)
########################## XRAM ###############################################
xram_addr_rx = ila.concat(bv(0, 8),
ila.choice('lsb_xram_addr', [rx[0], rx[1]]))
xram_addr_next = ila.choice('xram_addr',
[xram_addr_rx, dptr, uc.xram_addr,
bv(0, 16)])
model.set_next('XRAM_ADDR', xram_addr_next)
xram_data_out_next = ila.choice('xram_data_out', [bv(0, 8), acc])
model.set_next('XRAM_DATA_OUT', xram_data_out_next)
########################## SFRS ###############################################
sfrs = [
'p0', 'p1', 'p2', 'p3', 'pcon', 'tcon', 'tmod', 'tl0', 'th0', 'tl1',
'th1', 'scon', 'sbuf', 'ie', 'ip'
]
for s in sfrs:
sfr_next = ila.choice(
s + '_next',
[getattr(r_bit, s),
getattr(r_dir, s),
getattr(uc, s)])
model.set_next(s.upper(), sfr_next)
for s in state:
print s
st = time.clock()
model.synthesize(s, eval8051)
t_elapsed = time.clock() - st
ast = model.get_next(s)
print 'time: %.2f' % t_elapsed
model.exportOne(ast, 'asts/%s_%s' % (s, 'en' if enable_ps else 'dis'))
def ssa_next_state(self):
self.model.set_next('pc', self.pc + 4)
instruction_book_obj = open('instruction_book', 'r')
instruction_book = instruction_book_obj.readlines()
current_pc = 0
next_state_finished = []
for program_line in program:
if len(program_line) < 2:
continue
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
opcode_length = int(opcode_split[-1][1:])
current_pc_in = current_pc
if opcode_name == 'ld':
dest_type = ssa_declaration[program_line[1]]
addr_type = ssa_declaration[program_line[2]]
dest_length = int(dest_type[2:])
addr_length = int(addr_type[2:])
dest_reg = self.model.getreg(program_line[1])
addr_reg = self.model.getreg(program_line[2])
if dest_length > instruction_format.DMEM_BITS:
dest = ila.sign_extend(self.mem[addr_reg[(instruction_format.MEM_ADDRESS_BITS - 1) : 0]], dest_length)
elif dest_length == instruction_format.DMEM_BITS:
dest = self.mem[addr_reg[(instruction_format.MEM_ADDRESS_BITS - 1) : 0]]
else:
dest_interim = self.mem[addr_reg[(instruction_format.MEM_ADDRESS_BITS - 1) : 0]]
dest = dest_interim[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, dest, dest_reg))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'cvta':
dest_type = ssa_declaration[program_line[1]]
src_type = ssa_declaration[program_line[2]]
dest_length = int(dest_type[2:])
src_length = int(src_type[2:])
dest = self.model.getreg(program_line[1])
src = self.model.getreg(program_line[2])
if dest_length > src_length:
src = ila.sign_extend(src, dest_length)
if dest_length < src_length:
src = src[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, src, dest))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'mov':
dest_type = ssa_declaration[program_line[1]]
src_type = ssa_declaration[program_line[2]]
dest_length = int(dest_type[2:])
src_length = int(src_type[2:])
dest = self.model.getreg(program_line[1])
src = self.model.getreg(program_line[2])
if dest_length > src_length:
src = ila.sign_extend(src, dest_length)
if dest_length < src_length:
src = src[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, src, dest))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'add':
dest = self.model.getreg(program_line[1])
src0 = self.model.getreg(program_line[2])
src1 = self.model.getreg(program_line[3])
dest_type = ssa_declaration[program_line[1]]
src0_type = ssa_declaration[program_line[2]]
src1_type = ssa_declaration[program_line[3]]
dest_length = int(dest_type[2:])
src0_length = int(src0_type[2:])
src1_length = int(src1_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
if dest_length < src0_length:
src0 = src0[(dest_length - 1) : 0]
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
if dest_length < src1_length:
src1 = src1[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, src0 + src1, dest))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'mul':
dest_type = ssa_declaration[program_line[1]]
src0_type = ssa_declaration[program_line[2]]
dest_length = int(dest_type[2:])
src0_length = int(src0_type[2:])
dest = self.model.getreg(program_line[1])
src0 = self.model.getreg(program_line[2])
src1 = ila.const(int(program_line[3]), dest_length)
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
if dest_length < src0_length:
src0 = src0[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, src0 * src1, dest))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'st':
addr = self.model.getreg(program_line[1])
src = self.model.getreg(program_line[2])
self.model.set_next('mem', ila.ite(self.pc == current_pc,ila.store(self.mem, addr[(instruction_format.MEM_ADDRESS_BITS - 1):0], src[(instruction_format.DMEM_BITS - 1):0]), self.mem))
current_pc += 4
if current_pc == current_pc_in:
print program_line
a = self.model.reg('support', 32)
self.model.set_next('support', self.model.getreg('s3') + self.model.getreg('s1'))
for reg_name in ssa_declaration.keys():
if reg_name not in next_state_finished:
reg = self.model.getreg(reg_name)
self.model.set_next(reg_name, reg)
def generate_next_state(self, run_index, index):
self.mem_access_list = []
instruction_book_obj = open('instruction_book', 'r')
instruction_book = instruction_book_obj.readlines()
current_pc = 0
next_state_finished = []
pc_target = {}
current_pc = 0
for program_line in program:
if len(program_line) < 2:
if len(program_line) == 0:
continue
if program_line[0][-1] == ':':
pc_target[program_line[0][:-1]] = current_pc
else:
current_pc += 4
current_pc = 0
for program_line in program:
if len(program_line) < 2:
continue
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
#opcode_length = int(opcode_split[-1][1:])
current_pc_in = current_pc
if opcode_name == 'ld':
opcode_mem_type = opcode_split[1]
self.mem_access_list.append(current_pc)
dest_str = program_line[1]
addr_str = program_line[2]
imm_pos = addr_str.find(
'+') # a = 'ss+2' a.find('+'), a[:2], a[2 + 1:]
imm_str = '0'
if imm_pos != -1:
imm_str = addr_str[(imm_pos + 1):]
addr_str = addr_str[:imm_pos]
dest_type = ptx_declaration[dest_str]
addr_type = ptx_declaration[addr_str]
dest_length = int(dest_type[2:])
addr_length = int(addr_type[2:])
dest_reg = self.model.getreg(dest_str + '_%d_%d' %
(run_index, index))
addr_reg = self.model.getreg(addr_str + '_%d_%d' %
(run_index, index))
if addr_length >= instruction_format.MEM_ADDRESS_BITS:
address = addr_reg[(instruction_format.MEM_ADDRESS_BITS -
1):0]
else:
address = ila.sign_extend(
addr_reg, instruction_format.MEM_ADDRESS_BITS)
if dest_length > instruction_format.DMEM_BITS:
if opcode_mem_type == 'param':
#dest = ila.sign_extend(self.imem_list[run_index][address + ila.const(int(imm_str), instruction_format.MEM_ADDRESS_BITS)], dest_length)
continue
else:
dest = ila.sign_extend(
self.mem_list[run_index]
[address +
ila.const(int(imm_str),
instruction_format.MEM_ADDRESS_BITS)],
dest_length)
elif dest_length == instruction_format.DMEM_BITS:
if opcode_mem_type == 'param':
#dest = self.imem_list[run_index][address + ila.const(int(imm_str), instruction_format.MEM_ADDRESS_BITS)]
continue
else:
dest = self.mem_list[run_index][address + ila.const(
int(imm_str), instruction_format.MEM_ADDRESS_BITS)]
else:
if opcode_mem_type == 'param':
#dest_interim = self.imem_list[run_index][address + ila.const(int(imm_str), instruction_format.MEM_ADDRESS_BITS)]
continue
else:
dest_interim = self.mem_list[run_index][
address +
ila.const(int(imm_str),
instruction_format.MEM_ADDRESS_BITS)]
dest = dest_interim[(dest_length - 1):0]
self.next_state_dict[run_index][
dest_str + '_%d_%d' % (run_index, index)] = ila.ite(
self.pc_list[run_index][index] == current_pc, dest,
self.next_state_dict[run_index][dest_str + '_%d_%d' %
(run_index, index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'cvta':
dest_type = ptx_declaration[program_line[1]]
src_type = ptx_declaration[program_line[2]]
dest_length = int(dest_type[2:])
src_length = int(src_type[2:])
dest = self.model.getreg(program_line[1] + '_%d_%d' %
(run_index, index))
src = self.model.getreg(program_line[2] + '_%d_%d' %
(run_index, index))
if dest_length > src_length:
src = ila.sign_extend(src, dest_length)
if dest_length < src_length:
src = src[(dest_length - 1):0]
self.next_state_dict[run_index][
program_line[1] + '_%d_%d' % (run_index, index)] = ila.ite(
self.pc_list[run_index][index] == current_pc, src,
self.next_state_dict[run_index][program_line[1] +
'_%d_%d' %
(run_index, index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'mov':
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
dest = self.model.getreg(program_line[1] + '_%d_%d' %
(run_index, index))
src_str = program_line[2]
if src_str in ptx_declaration.keys():
src = self.model.getreg(src_str + '_%d_%d' %
(run_index, index))
src_type = ptx_declaration[program_line[2]]
src_length = int(src_type[2:])
if dest_length > src_length:
src = ila.sign_extend(src, dest_length)
if dest_length < src_length:
src = src[(dest_length - 1):0]
else:
src = ila.const(int(src_str), dest_length)
self.next_state_dict[run_index][
program_line[1] + '_%d_%d' % (run_index, index)] = ila.ite(
self.pc_list[run_index][index] == current_pc, src,
self.next_state_dict[run_index][program_line[1] +
'_%d_%d' %
(run_index, index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'add':
dest = self.model.getreg(program_line[1] + '_%d_%d' %
(run_index, index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d_%d' %
(run_index, index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d_%d' %
(run_index, index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1 = ila.const(int(src1_str), dest_length)
self.next_state_dict[run_index][
program_line[1] + '_%d_%d' % (run_index, index)] = ila.ite(
self.pc_list[run_index][index] == current_pc,
src0 + src1,
self.next_state_dict[run_index][program_line[1] +
'_%d_%d' %
(run_index, index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'mul':
dest = self.model.getreg(program_line[1] + '_%d_%d' %
(run_index, index))
dest_type = ptx_declaration[program_line[1]]
dest_length = int(dest_type[2:])
src0_str = program_line[2]
if src0_str in ptx_declaration.keys():
src0 = self.model.getreg(src0_str + '_%d_%d' %
(run_index, index))
src0_type = ptx_declaration[src0_str]
src0_length = int(src0_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
elif dest_length < src0_length:
src0 = src0[(dest_length - 1):0]
else:
src0 = ila.const(int(src0_str), dest_length)
src1_str = program_line[3]
if src1_str in ptx_declaration.keys():
src1 = self.model.getreg(src1_str + '_%d_%d' %
(run_index, index))
src1_type = ptx_declaration[src1_str]
src1_length = int(src1_type[2:])
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
elif dest_length < src1_length:
src1 = src1[(dest_length - 1):0]
else:
src1 = ila.const(int(src1_str), dest_length)
self.next_state_dict[run_index][
program_line[1] + '_%d_%d' % (run_index, index)] = ila.ite(
self.pc_list[run_index][index] == current_pc,
src0 * src1,
self.next_state_dict[run_index][program_line[1] +
'_%d_%d' %
(run_index, index)])
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'st':
self.mem_access_list.append(current_pc)
src_str = program_line[2]
addr_str = program_line[1]
imm_pos = addr_str.find(
'+') # a = 'ss+2' a.find('+'), a[:2], a[2 + 1:]
imm_str = '0'
if imm_pos != -1:
imm_str = addr[(imm_pos + 1):]
addr_str = addr_str[:imm_pos]
src_type = ptx_declaration[src_str]
addr_type = ptx_declaration[addr_str]
src_length = int(src_type[2:])
addr_length = int(addr_type[2:])
src = self.model.getreg(src_str + '_%d_%d' %
(run_index, index))
addr = self.model.getreg(addr_str + '_%d_%d' %
(run_index, index))
self.mem_next_state_list[run_index] = ila.ite(
(self.pc_list[run_index][index] == current_pc) &
(self.arb_list[run_index]
== self.arb_choice_list[run_index][index]),
ila.store(
self.mem_list[run_index],
addr[(instruction_format.MEM_ADDRESS_BITS - 1):0] +
ila.const(int(imm_str),
instruction_format.MEM_ADDRESS_BITS), src),
self.mem_next_state_list[run_index])
current_pc += 4
if current_pc == current_pc_in:
print program_line
#a = self.model.reg('support', 32)
#self.model.set_next('support', self.model.getreg('s3') + self.model.getreg('s1'))
for reg_name in ptx_declaration.keys():
if reg_name not in next_state_finished:
reg = self.model.getreg(reg_name + '_%d_%d' %
(run_index, index))
self.model.set_next(reg_name + '_%d_%d' % (run_index, index),
reg)
self.pc_max = current_pc
def create_data_race_element(self, access_set, pred_map, log):
if log == True:
suffix = 'log'
index = 0
else:
suffix = 'check'
index = 1
self.log_clean = ila.bool(False)
self.check_clean = ila.bool(False)
for pc in self.bar_list:
bar_pred_list = self.pred_map[pc]
conj_bar_pred = self.pred_gen(index, bar_pred_list)
self.log_clean = self.log_clean | ((self.pc_list[0] == pc) &
(conj_bar_pred))
self.check_clean = self.check_clean | ((self.pc_list[0] == pc) &
(conj_bar_pred))
for pc in access_set.keys():
reg_name = access_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (index)),
reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' %
(index))
else:
operands[i] = self.aux_imm(operand, 0, reg_len)
access_reg_next = operands[0]
for i in range(1, len(operands)):
access_reg_next = access_reg_next + operands[i]
en_access_reg_next = ila.const(0x1, 1)
en_access_reg_clear = ila.const(0x0, 1)
pred_list = self.pred_map[pc]
conj_pred = self.pred_gen(index, pred_list)
#if log:
# self.model.set_next(reg_name + '_en_%s_%d' % (suffix, pc), ila.ite(self.pc_list[index] == pc, en_access_reg_next, ila.ite(self.log_clean, ila.const(0x0, 1), en_access_reg)))
#else:
# self.model.set_next(reg_name + '_en_%s_%d' % (suffix, pc), ila.ite(self.pc_list[index] == pc, en_access_reg_next, ila.ite(self.check_clean, ila.const(0x0, 1), en_access_reg)))
if log:
self.log_register_next = ila.ite(
(self.pc_list[0] == pc) & (self.arb_list[index] == 1),
access_reg_next, self.log_register_next)
self.en_log_register_next = ila.ite(
(self.pc_list[0] == pc) & (self.arb_list[index] == 1) &
(conj_pred), en_access_reg_next, self.en_log_register_next)
#self.log_register_next = ila.ite(self.pc_list[index] == pc, ila.ite(self.arb_list[index] == 1, access_reg_next, self.log_register_next), self.log_register_next)
#self.en_log_register_next = ila.ite(self.pc_list[index] == pc, ila.ite((self.arb_list[index] == 1) & (conj_pred), en_access_reg_next, self.en_log_register_next), self.en_log_register_next)
else:
self.check_register_next = ila.ite(
(self.pc_list[0] == pc) & (self.arb_list[index] == 1),
access_reg_next, self.check_register_next)
self.en_check_register_next = ila.ite(
(self.pc_list[0] == pc) & (self.arb_list[index] == 1) &
(conj_pred), en_access_reg_next,
self.en_check_register_next)
#self.check_register_next = ila.ite(self.pc_list[index] == pc, ila.ite(self.arb_list[index] == 1, access_reg_next, self.check_register_next), self.check_register_next)
#self.en_check_register_next = ila.ite(self.pc_list[index] == pc, ila.ite((self.arb_list[index] == 1) & (conj_pred), en_access_reg_next, self.en_check_register_next), self.en_check_register_next)
if log:
self.en_log_register_next = ila.ite(self.log_clean,
ila.const(0x0, 1),
self.en_log_register_next)
else:
self.en_check_register_next = ila.ite(self.check_clean,
ila.const(0x0, 1),
self.en_check_register_next)
def sext(self,v):
return ila.sign_extend(v,XLEN)
