def __init__(self, app_name, app_prefix):
self.app_name = app_name
inst_db_file = app_prefix + '_parsed.txt'
# get instruction database of application
inst_db = open(inst_db_file).read().splitlines()
# first field is ignored since it contains only headers
self.insts = [instruction(None, None, i) for i in inst_db[1:]]
self.insts_map = {inst.pc: inst for inst in self.insts}
# get trace data to build basic blocks and store equiv classes
# self.exec_trace = trace(mem_filename)
self.trace_filename = app_prefix + '_clean_dump_parsed_merged.txt'
# used to check alias of register when creating dependency chains
self.x86_regs = x86_register()
self.basic_blocks_map = {}
self.st_inst_pcs = set()
self.ld_inst_pcs = set()
self.dep_insts = depending_instructions()
self.static_st_inst_map = {}
self.addr_map = {} # holds info on latest store accessing an address
def print_node_more_attribs(self, dis_parsed_file):
'''
add more attributes for nodes
'''
db_info = [i for i in open(dis_parsed_file).read().splitlines()[1:]]
insts = [instruction(None, None, i) for i in db_info]
for i in insts:
if i.pc == self.pc:
return '%s %s %s %s %s %s %s %s %s %s %s %s %r' % (
self.name, self.pc, i.op, self.isa, self.tick, self.reg,
self.bit, self.reg_type, self.src_dest, self.str_ctl,
self.inj, self.category, self.label)
def __init__(self,app_name,inst_db_filename,create_inst_db=False):
insts = []
if create_inst_db:
dis_filename = inst_db_filename
inst_db = inst_database(dis_filename)
insts = inst_database.insts
else:
db_file = inst_db_filename
# read and organize disassembly info (1st line is just header)
db_info = [i for i in open(db_file).read().splitlines()[1:]]
insts = [instruction(None,None,i) for i in db_info]
pc_list = [inst.pc for inst in insts]
pc_def_map = {}
x86_regs = x86_register()
x86_active_regs = x86_reg_collection()
for inst in insts:
pc = inst.pc
is_ctrl_op = inst.ctrl_flag
src_regs = inst.src_regs + inst.mem_src_regs
dest_reg = inst.dest_reg
if is_ctrl_op: # reset map once leaving basic block
x86_active_regs.clear_regs()
else:
for i in range(len(src_regs)):
src_reg = src_regs[i]
alias_reg = x86_regs.reg_alias_map[src_reg]
alias_dest_reg = x86_active_regs[alias_reg]
src_reg_size = x86_regs.reg_size_map[src_reg]
# check for registers such as 'ah'
if src_reg_size == -1:
bit_range_pc = alias_dest_reg.bit_ranges[1]
if bit_range_pc is not None:
pc_def_map[bit_range_pc].update_first_use(1, pc)
else:
for j in range(src_reg_size):
bit_range_pc = alias_dest_reg.bit_ranges[j]
if bit_range_pc is not None:
pc_def_map[bit_range_pc].update_first_use(j, pc)
if dest_reg is not None:
pc_def_map[pc]=x86_def_register(dest_reg, pc)
alias_reg = x86_regs.reg_alias_map[dest_reg]
x86_active_regs[alias_reg].update_def(dest_reg, pc)
self.pc_list = pc_list
self.pc_def_map = pc_def_map
def print_node_more_attribs(self, dis_parsed_file):
'''
add more attributes for nodes
'''
db_info = [i for i in open(dis_parsed_file).read().splitlines()[1:]]
insts = [instruction(None, None, i) for i in db_info]
for i in insts:
if i.pc == self.pc:
for j in i.src_regs:
if self.reg == j:
self.type = 'SRC'
break
for j in i.mem_src_regs:
if self.reg == j:
self.type = 'MEM_SRC'
break
if self.reg == i.dest_reg:
self.type = 'DEST'
return '%s %s %s %s %s %r' % (self.name, self.pc, self.reg,
self.type, i.op, self.label)
def print_node_more_attribs(self, dis_parsed_file):
'''
add more attributes for nodes
'''
db_info = [i for i in open(dis_parsed_file).read().splitlines()[1:]]
insts = [instruction(None, None, i) for i in db_info]
for i in insts:
src_regs = i.src_regs
mem_src_regs = i.mem_src_regs
if len(src_regs) == 0:
src_regs = 'None'
else:
src_regs = ','.join(src_regs)
if len(mem_src_regs) == 0:
mem_src_regs = 'None'
else:
mem_src_regs = ','.join(mem_src_regs)
dest_reg = i.dest_reg
if dest_reg is None:
dest_regi = 'None'
if i.ctrl_flag == True:
ctrl_flag = 1
else:
ctrl_flag = 0
if i.is_mem == True:
is_mem = 1
else:
is_mem = 0
if i.pc == self.pc:
self.opcode = i.op
#return '%s %s %s %r %s %s %r %s %d %r' % (
#self.name, self.pc, i.op, i.ctrl_flag, src_regs, mem_src_regs, i.is_mem, dest_reg, i.max_bits,self.label)
return '%s %s %d %d %d %f %f %f %f ' % (
app_name + '_' + str(self.name), i.op, ctrl_flag, i.is_mem,
i.max_bits, self.weight, self.mask, self.sdc, self.crash)
if len(sys.argv) != 3:
print('Usage: python control_equivalence.py [app_name] [isa]')
exit()
app_name = sys.argv[1]
isa = sys.argv[2]
approx_dir = os.environ.get('APPROXGEM5')
apps_dir = approx_dir + '/workloads/' + isa + '/apps/' + app_name
app_prefix = apps_dir + '/' + app_name
db_filename = app_prefix + '_parsed.txt'
trace_filename = app_prefix + '_clean_dump_parsed_merged.txt'
db_info = [i for i in open(db_filename).read().splitlines()[1:]]
insts = [instruction(None, None, i) for i in db_info]
ctrl_insts = set([i.pc for i in insts if i.ctrl_flag])
# list of basic blocks. Each list element is a 2-length list with
# first element as start PC and second as end PC
basicblocks = set() # defaultdict(int)
# program represented as basic blocks with tick value at start of basic block
program_bb = []
with open(trace_filename) as trace:
bbstart = None
bbend = None
start_of_bb = True
pc = None
prev_pc = pc
for line in trace:
def __init__(self, app_name, apps_dir):
self.app_name = app_name
ignored_ops = {'prefetch'}
app_prefix = apps_dir + '/' + app_name
trace_file = app_prefix + '_clean_dump_parsed_merged.txt'
ctrl_equiv_file = app_prefix + '_control_equivalence.txt'
store_equiv_file = app_prefix + '_store_equivalence.txt'
dep_stores_file = app_prefix + '_dependent_stores.txt'
def_use_file = app_prefix + '_def_use.txt'
db_file = app_prefix + '_parsed.txt'
ctrl_equiv_info = [
i.split(':')[0:3]
for i in open(ctrl_equiv_file).read().splitlines()[1:]
]
store_equiv_info = [
i.split(':')[0:3]
for i in open(store_equiv_file).read().splitlines()[1:]
]
self.def_use_info = {
i.split()[0]: simple_def_reg(i.split()[1],
i.split()[2:6])
for i in open(def_use_file).read().splitlines()[1:]
}
store_equiv_pilots = set([i[2] for i in store_equiv_info])
dep_stores_list = open(dep_stores_file).read().splitlines()[1:]
dep_stores_info = {}
for item in dep_stores_list:
temp = item.split()
dep_pc = temp[0]
store_pc = temp[1]
if store_pc not in dep_stores_info:
dep_stores_info[store_pc] = []
dep_stores_info[store_pc].append(dep_pc)
store_equiv_pcs = set()
db_info = [i for i in open(db_file).read().splitlines()[1:]]
insts = [instruction(None, None, i) for i in db_info]
self.inst_db_map = {i.pc: i for i in insts}
self.ctrl_insts = set([i.pc for i in insts if i.ctrl_flag])
# trace_info = trace(trace_file)
self.pc_map = {}
pc_idx = 0
pilot_idx = 2
member_idx = 3
# new_store_equiv_file = app_prefix + '_final_store_equivalence.txt'
# new_ctrl_equiv_file = app_prefix + '_final_control_equivalence.txt'
dep_stores_equiv_classes = []
dep_stores_pilot_map = {}
for item in store_equiv_info:
pc = item[pc_idx]
pilot = item[pilot_idx]
# members = item[member_idx].split()
self._add_to_pc_map(pc, pilot, 'store')
store_equiv_pcs.add(pc)
with open(trace_file) as f:
curr_bb = {}
for line in f:
item = trace_item(line.split())
if item.pc in self.ctrl_insts:
curr_bb = {}
curr_bb[item.pc] = item.inst_num
# store that depends on prev insts
if item.inst_num in store_equiv_pilots and item.pc in dep_stores_info:
for dep_pc in dep_stores_info[item.pc]:
if dep_pc in curr_bb:
self._add_to_pc_map(dep_pc, curr_bb[dep_pc],
'store')
store_equiv_pcs.add(dep_pc)
# build non-store pc equivalence classes for
# store equivalence (previously in control_equiv file)
# if pc in dep_stores_info:
# for dep_pc in dep_stores_info[pc]:
# dep_pc_pilot = ''
# dep_pc_equiv = equiv_class(dep_pc)
# is_ctrl = False
# for member in members:
# store_idx = trace_info.get_idx(member)
# added_to_pc_map = False
# for i in range(store_idx,-1,-1):
# trace_item = trace_info[i]
# is_ctrl = self.inst_db_map[
# trace_item.pc].ctrl_flag
# if is_ctrl:
# if dep_pc in store_equiv_pcs:
# store_equiv_pcs.remove(dep_pc)
# if added_to_pc_map:
# self._remove_from_pc_map(dep_pc)
# dep_stores_info[pc].remove(dep_pc)
# break
# if trace_item.pc == dep_pc:
# if member == pilot:
# dep_pc_pilot = trace_item.inst_num
# self._add_to_pc_map(dep_pc,dep_pc_pilot,
# 'store')
# added_to_pc_map = True
# store_equiv_pcs.add(dep_pc)
# dep_pc_equiv.add_member(
# trace_item.inst_num)
# break
# if is_ctrl:
# break
# dep_pc_equiv.set_pilot(dep_pc_pilot)
# if not is_ctrl:
# dep_stores_equiv_classes.append(dep_pc_equiv)
# new_ctrl_info = [] # stores pcs that stores do not depend on
for item in ctrl_equiv_info:
pc = item[pc_idx]
pilot = item[pilot_idx]
if pc not in store_equiv_pcs:
self._add_to_pc_map(pc, pilot, 'ctrl')
# new_ctrl_info.append(item)
# update final equivalence class files
# with open(new_ctrl_equiv_file, 'w') as f:
# for item in new_ctrl_info:
# f.write('%s\n' % ':'.join(item))
# del new_ctrl_info
#
# shutil.copy(store_equiv_file,new_store_equiv_file)
# with open(new_store_equiv_file, 'a') as f:
# for item in dep_stores_equiv_classes:
# f.write('%s\n' % item.print_equiv_class())
# del dep_stores_equiv_classes
self.pc_list = sorted(self.pc_map.keys())