def bench_dct_2d():
tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, stage_1_prec,
output_bits, N)
tbclock = clock_driver(clock)
@instance
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for j in in_out_data.inputs[i]:
for k in j:
inputs.data_in.next = k
yield clock.posedge
@instance
def monitor():
outputs_count = 0
while outputs_count != samples:
yield clock.posedge
yield delay(1)
if outputs.data_valid:
out_print(in_out_data.outputs[outputs_count],
outputs.out_sigs, N)
outputs_count += 1
raise StopSimulation
return tdut, tbclock, tbstim, monitor
def bench_dct_2d():
tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, stage_1_prec,
output_bits, N)
tbclock = clock_driver(clock)
@instance
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for j in in_out_data.inputs[i]:
for k in j:
inputs.data_in.next = k
yield clock.posedge
@instance
def monitor():
outputs_count = 0
while outputs_count != samples:
yield clock.posedge
yield delay(1)
if outputs.data_valid:
out_print(in_out_data.outputs[outputs_count],
outputs.out_sigs, N)
outputs_count += 1
raise StopSimulation
return tdut, tbclock, tbstim, monitor
def bench_dct_2d():
tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, output_bits,
stage_1_prec, N)
tbclk = clock_driver(clock)
tbrst = reset_on_start(reset, clock)
print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
@instance
def tbstim():
yield reset.negedge
inputs.data_valid.next =True
for i in range(samples * (N**2)):
inputs.data_in.next = inputs_rom[i]
yield clock.posedge
print_assign = outputs.assignment_2(print_sig_1)
@instance
def monitor():
outputs_count = 0
while outputs_count != samples:
yield clock.posedge
if outputs.data_valid:
for i in range(N**2):
print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i]
yield delay(1)
print("Expected Outputs")
for i in range(N**2):
print("%d " % print_sig[i])
print("Actual Outputs")
for i in range(N**2):
print("%d " % print_sig_1[i])
print("------------------------------")
outputs_count += 1
raise StopSimulation
return tdut, tbclk, tbstim, monitor, tbrst, print_assign
def bench_dct_2d():
tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, output_bits,
stage_1_prec, N)
tbclk = clock_driver(clock)
tbrst = reset_on_start(reset, clock)
print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
@instance
def tbstim():
yield reset.negedge
inputs.data_valid.next =True
for i in range(samples * (N**2)):
inputs.data_in.next = inputs_rom[i]
yield clock.posedge
print_assign = assign_array(print_sig_1, outputs.out_sigs)
@instance
def monitor():
outputs_count = 0
while outputs_count != samples:
yield clock.posedge
if outputs.data_valid:
for i in range(N**2):
print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i]
yield delay(1)
print("Expected Outputs")
for i in range(N**2):
print("%d " % print_sig[i])
print("Actual Outputs")
for i in range(N**2):
print("%d " % print_sig_1[i])
print("------------------------------")
outputs_count += 1
raise StopSimulation
return tdut, tbclk, tbstim, monitor, tbrst, print_assign