Exemplo n.º 1
0
    def bench_rle_core():
        """The conversion module for rle core"""
        inst = rle(
            clock, reset,
            datastream, rlesymbols, rleconfig
            )
        inst_clock = clock_driver(clock)
        inst_reset = reset_on_start(reset, clock)

        @instance
        def tbstim():
            """dummy inputs for conversion purpose"""
            yield clock.posedge
            print ("Conversion done!!")
            raise StopSimulation

        return tbstim, inst, inst_clock, inst_reset
Exemplo n.º 2
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    def bench_rle_core():
        """The conversion module for rle core"""
        inst = rle(
            clock, reset,
            datastream, rlesymbols, rleconfig
            )
        inst_clock = clock_driver(clock)
        inst_reset = reset_on_start(reset, clock)

        @instance
        def tbstim():
            """dummy inputs for conversion purpose"""
            yield clock.posedge
            print ("Conversion done!!")
            raise StopSimulation

        return tbstim, inst, inst_clock, inst_reset
Exemplo n.º 3
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    def bench_rle_core():
        """The RLE Core is tested in this block"""

        # instantiation of the rle core
        inst = rle(
            clock, reset, datastream, rlesymbols, rleconfig
            )

        # clock instantiation
        inst_clock = clock_driver(clock)

        @instance
        def tbstim():
            """Test inputs given here"""

            # reset before sending data
            yield pulse_reset(reset, clock)

            # components of type y1 or y2 processed
            yield block_process(
                clock, red_pixels_1,
                datastream,
                rlesymbols,
                rleconfig, component.y1_space, max_count=max_addr_cnt
                )

            print ("======================")

            # components of type y1 or y2 processed
            yield block_process(
                clock, red_pixels_2,
                datastream,
                rlesymbols,
                rleconfig, component.y2_space, max_count=max_addr_cnt
                )

            print ("=====================")

            # components of type cb processes
            yield block_process(
                clock, green_pixels_1,
                datastream,
                rlesymbols,
                rleconfig, component.cb_space, max_count=max_addr_cnt
                )

            print ("=====================")

            # components od type cb processed
            yield block_process(
                clock, green_pixels_2,
                datastream,
                rlesymbols,
                rleconfig, component.cb_space, max_count=max_addr_cnt
                )

            print ("=====================")

            # components of type cr processed
            yield block_process(
                clock, blue_pixels_1,
                datastream,
                rlesymbols,
                rleconfig, component.cr_space, max_count=max_addr_cnt
                )

            print ("=====================")

            # components of type cr processed
            yield block_process(
                clock, blue_pixels_2,
                datastream,
                rlesymbols,
                rleconfig, component.cr_space, max_count=max_addr_cnt
                )

            print ("=====================")

            # start of new frame asserts
            rleconfig.sof.next = True
            yield clock.posedge

            raise StopSimulation

        return tbstim, inst_clock, inst
Exemplo n.º 4
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def rlencoder(clock, reset, datastream, bufferdatabus, rleconfig):
    """
    The top module connects rle core and rle double buffer

    I/O Ports:

    datastream      : input datastream bus
    buffer data bus : output data bus
    rleconfig       : configuration bus

    Constants:

    width_data      : input data width
    width_addr      : address width
    width_size      : width of register to store amplitude size
    max_addr_cnt    : maximum address of the block being processed
    width_runlength : width of runlength value that can be stored
    limit           : value of maximum runlength value
    width_depth     : width of the FIFO Bus

    """

    assert isinstance(datastream, DataStream)
    assert isinstance(bufferdatabus, BufferDataBus)
    assert isinstance(rleconfig, RLEConfig)

    # width of input data
    width_data = len(datastream.data_in)

    # width of the address register
    width_addr = len(datastream.read_addr)

    # width of register to store amplitude size
    width_size = len(bufferdatabus.size)

    # width to store the runlength value
    width_runlength = len(bufferdatabus.runlength)

    # maximum address of block
    max_addr_cnt = int((2**(width_addr)) - 1)

    # depth of the FIFO
    width_depth = max_addr_cnt + 1

    # Signals used to temporarily process data
    rlesymbols_temp = RLESymbols(
        width_data, width_size, width_runlength)
    assert isinstance(rlesymbols_temp, RLESymbols)

    # maximum number of zeroes that can be count
    limit = int((2**width_runlength) - 1)

    # width of data to be stored in rle double fifo
    width_dbuf_data = width_data + width_size + width_runlength

    # instantiation of double buffer bus
    dfifo = FIFOBus(width_dbuf_data)
    assert isinstance(dfifo, FIFOBus)

    buffer_sel = Signal(bool(0))

    # maximum number of pixels that can be processes for one time
    wr_cnt = Signal(modbv(0)[width_addr:])

    @always_comb
    def assign0():
        """assign data to the output bus"""

        buffer_sel.next = bufferdatabus.buffer_sel
        dfifo.read.next = bufferdatabus.read_enable
        bufferdatabus.fifo_empty.next = dfifo.empty

    @always_comb
    def assign1():
        """runlength, size and amplitude read from double buffer"""

        bufferdatabus.runlength.next = dfifo.read_data[(
            width_data+width_size+width_runlength):(
            width_data+width_size)]

        bufferdatabus.size.next = dfifo.read_data[(
            width_data+width_size):width_data]

        bufferdatabus.amplitude.next = dfifo.read_data[width_data:0].signed()

    # send the inputdata into rle core
    rle_core = rle(clock, reset, datastream, rlesymbols_temp, rleconfig)

    # write the processed data to rle double fifo
    rle_doublefifo = doublefifo(
        clock, reset, dfifo, buffer_sel, depth=width_depth)

    @always_comb
    def assign3():
        """write data into the FIFO Bus"""

        dfifo.write_data.next = concat(
            rlesymbols_temp.runlength, rlesymbols_temp.size,
            rlesymbols_temp.amplitude)

        dfifo.write.next = rlesymbols_temp.dovalid

    @always_seq(clock.posedge, reset=reset)
    def seq1():
        """process the block using rlecore"""

        rleconfig.ready.next = False
        if rleconfig.start:
            wr_cnt.next = 0

        # select the data to be written
        if rlesymbols_temp.dovalid:
            if (rlesymbols_temp.runlength == limit) and (
                    rlesymbols_temp.size == 0):

                wr_cnt.next = wr_cnt + limit + 1

            else:
                wr_cnt.next = wr_cnt + 1 + rlesymbols_temp.runlength

            if dfifo.write_data == 0 and wr_cnt != 0:
                rleconfig.ready.next = True
            else:
                if (wr_cnt + rlesymbols_temp.runlength) == max_addr_cnt:
                    rleconfig.ready.next = True

    @always_seq(clock.posedge, reset=reset)
    def assign3_buf():
        """Input buffer selection"""
        if rleconfig.start:
            datastream.buffer_sel.next = not datastream.buffer_sel

    @always_comb
    def assign4():
        """output data valid signal generation"""
        bufferdatabus.dovalid.next = bufferdatabus.read_enable

    return (assign0, assign1, rle_core, rle_doublefifo,
            assign3, seq1, assign3_buf, assign4)
Exemplo n.º 5
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def rlencoder(clock, reset, datastream, bufferdatabus, rleconfig):
    """
    The top module connects rle core and rle double buffer

    I/O Ports:

    datastream      : input datastream bus
    buffer data bus : output data bus
    rleconfig       : configuration bus

    Constants:

    width_data      : input data width
    width_addr      : address width
    width_size      : width of register to store amplitude size
    max_addr_cnt    : maximum address of the block being processed
    width_runlength : width of runlength value that can be stored
    limit           : value of maximum runlength value
    width_depth     : width of the FIFO Bus

    """

    assert isinstance(datastream, DataStream)
    assert isinstance(bufferdatabus, BufferDataBus)
    assert isinstance(rleconfig, RLEConfig)

    # width of input data
    width_data = len(datastream.data_in)

    # width of the address register
    width_addr = len(datastream.read_addr)

    # width of register to store amplitude size
    width_size = len(bufferdatabus.size)

    # width to store the runlength value
    width_runlength = len(bufferdatabus.runlength)

    # maximum address of block
    max_addr_cnt = int((2**(width_addr)) - 1)

    # depth of the FIFO
    width_depth = max_addr_cnt + 1

    # Signals used to temporarily process data
    rlesymbols_temp = RLESymbols(width_data, width_size, width_runlength)
    assert isinstance(rlesymbols_temp, RLESymbols)

    # maximum number of zeroes that can be count
    limit = int((2**width_runlength) - 1)

    # width of data to be stored in rle double fifo
    width_dbuf_data = width_data + width_size + width_runlength

    # instantiation of double buffer bus
    dfifo = FIFOBus(width_dbuf_data)
    assert isinstance(dfifo, FIFOBus)

    buffer_sel = Signal(bool(0))

    # maximum number of pixels that can be processes for one time
    wr_cnt = Signal(modbv(0)[width_addr:])

    @always_comb
    def assign0():
        """assign data to the output bus"""

        buffer_sel.next = bufferdatabus.buffer_sel
        dfifo.read.next = bufferdatabus.read_enable
        bufferdatabus.fifo_empty.next = dfifo.empty

    @always_comb
    def assign1():
        """runlength, size and amplitude read from double buffer"""

        bufferdatabus.runlength.next = dfifo.read_data[(
            width_data + width_size + width_runlength):(width_data +
                                                        width_size)]

        bufferdatabus.size.next = dfifo.read_data[(width_data +
                                                   width_size):width_data]

        bufferdatabus.amplitude.next = dfifo.read_data[width_data:0].signed()

    # send the inputdata into rle core
    rle_core = rle(clock, reset, datastream, rlesymbols_temp, rleconfig)

    # write the processed data to rle double fifo
    rle_doublefifo = doublefifo(clock,
                                reset,
                                dfifo,
                                buffer_sel,
                                depth=width_depth)

    @always_comb
    def assign3():
        """write data into the FIFO Bus"""

        dfifo.write_data.next = concat(rlesymbols_temp.runlength,
                                       rlesymbols_temp.size,
                                       rlesymbols_temp.amplitude)

        dfifo.write.next = rlesymbols_temp.dovalid

    @always_seq(clock.posedge, reset=reset)
    def seq1():
        """process the block using rlecore"""

        rleconfig.ready.next = False
        if rleconfig.start:
            wr_cnt.next = 0

        # select the data to be written
        if rlesymbols_temp.dovalid:
            if (rlesymbols_temp.runlength == limit) and (rlesymbols_temp.size
                                                         == 0):

                wr_cnt.next = wr_cnt + limit + 1

            else:
                wr_cnt.next = wr_cnt + 1 + rlesymbols_temp.runlength

            if dfifo.write_data == 0 and wr_cnt != 0:
                rleconfig.ready.next = True
            else:
                if (wr_cnt + rlesymbols_temp.runlength) == max_addr_cnt:
                    rleconfig.ready.next = True

    @always_seq(clock.posedge, reset=reset)
    def assign3_buf():
        """Input buffer selection"""
        if rleconfig.start:
            datastream.buffer_sel.next = not datastream.buffer_sel

    @always_comb
    def assign4():
        """output data valid signal generation"""
        bufferdatabus.dovalid.next = bufferdatabus.read_enable

    return (assign0, assign1, rle_core, rle_doublefifo, assign3, seq1,
            assign3_buf, assign4)
Exemplo n.º 6
0
    def bench_rle_core():
        """The RLE Core is tested in this block"""

        # instantiation of the rle core
        inst = rle(
            clock, reset, datastream, rlesymbols, rleconfig
            )

        # clock instantiation
        inst_clock = clock_driver(clock)

        @instance
        def tbstim():
            """Test inputs given here"""

            # reset before sending data
            yield pulse_reset(reset, clock)

            # components of type y1 or y2 processed
            yield block_process(
                clock, red_pixels_1,
                datastream,
                rlesymbols,
                rleconfig, component.y1_space, max_count=max_addr_cnt
                )

            print ("======================")

            # components of type y1 or y2 processed
            yield block_process(
                clock, red_pixels_2,
                datastream,
                rlesymbols,
                rleconfig, component.y2_space, max_count=max_addr_cnt
                )

            print ("=====================")

            # components of type cb processes
            yield block_process(
                clock, green_pixels_1,
                datastream,
                rlesymbols,
                rleconfig, component.cb_space, max_count=max_addr_cnt
                )

            print ("=====================")

            # components od type cb processed
            yield block_process(
                clock, green_pixels_2,
                datastream,
                rlesymbols,
                rleconfig, component.cb_space, max_count=max_addr_cnt
                )

            print ("=====================")

            # components of type cr processed
            yield block_process(
                clock, blue_pixels_1,
                datastream,
                rlesymbols,
                rleconfig, component.cr_space, max_count=max_addr_cnt
                )

            print ("=====================")

            # components of type cr processed
            yield block_process(
                clock, blue_pixels_2,
                datastream,
                rlesymbols,
                rleconfig, component.cr_space, max_count=max_addr_cnt
                )

            print ("=====================")

            # start of new frame asserts
            rleconfig.sof.next = True
            yield clock.posedge

            raise StopSimulation

        return tbstim, inst_clock, inst