def __init__(self):
self.write_user_port = LiteDRAMWritePort(aw=32, dw=32)
self.write_crossbar_port = LiteDRAMWritePort(aw=32, dw=128)
self.submodules.write_converter = LiteDRAMPortConverter(self.write_user_port,
self.write_crossbar_port)
self.read_user_port = LiteDRAMReadPort(aw=32, dw=32)
self.read_crossbar_port = LiteDRAMReadPort(aw=32, dw=128)
self.submodules.read_converter = LiteDRAMPortConverter(self.read_user_port,
self.read_crossbar_port)
self.memory = DRAMMemory(128, 128)
def __init__(self):
self.write_port = LiteDRAMWritePort(aw=32, dw=32)
self.read_port = LiteDRAMReadPort(aw=32, dw=32)
self.submodules.generator = LiteDRAMBISTGenerator(self.write_port,
random=True)
self.submodules.checker = LiteDRAMBISTChecker(self.read_port,
random=True)
def __init__(self):
# write port and converter
self.write_user_port = LiteDRAMWritePort(aw=32, dw=32)
self.write_crossbar_port = LiteDRAMWritePort(aw=32, dw=128)
write_converter = LiteDRAMPortConverter(self.write_user_port,
self.write_crossbar_port)
self.submodules += write_converter
# read port and converter
self.read_user_port = LiteDRAMReadPort(aw=32, dw=32)
self.read_crossbar_port = LiteDRAMReadPort(aw=32, dw=128)
read_converter = LiteDRAMPortConverter(self.read_user_port,
self.read_crossbar_port)
self.submodules += read_converter
# memory
self.memory = DRAMMemory(128, 128)