def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, with_uart=False, **kwargs)
# Memory test BIST
self.submodules.generator = LiteDRAMBISTGenerator(
self.sdram.crossbar.get_port(mode="write", data_width=32))
self.submodules.checker = LiteDRAMBISTChecker(
self.sdram.crossbar.get_port(mode="read", data_width=32))
self.submodules.checker_scope = LiteDRAMBISTCheckerScope(self.checker)
# Litescope for analyzing the BIST output
# --------------------
# Dummy UART
self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200)
self.submodules.uart = self.suart.uart
self.submodules.uartbridge = UARTWishboneBridge(
platform.request("serial"), self.clk_freq, baudrate=19200)
self.add_wb_master(self.uartbridge.wishbone)
# self.submodules.io = LiteScopeIO(8)
# for i in range(8):
# try:
# self.comb += platform.request("user_led", i).eq(self.io.output[i])
# except:
# pass
analyzer_signals = self.checker_scope.signals()
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 64)
def __init__(self, platform, **kwargs):
clk_freq = 100 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="NeTV2 LiteX Base SoC",
**kwargs)
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 8)
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# sdram bist
generator_port = self.sdram.crossbar.get_port(mode="write")
self.submodules.generator = LiteDRAMBISTGenerator(generator_port)
checker_port = self.sdram.crossbar.get_port(mode="read")
self.submodules.checker = LiteDRAMBISTChecker(checker_port)
def __init__(self, platform):
sys_clk_freq = int(75e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x6000)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDRAM ------------------------------------------------------------------------------------
# phy
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
# module
sdram_module = M12L64322A(sys_clk_freq, "1:1")
# controller
self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
# bist
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.add_csr("sdram_checker")
# Led --------------------------------------------------------------------------------------
counter = Signal(32)
self.sync += counter.eq(counter + 1)
self.comb += platform.request("user_led").eq(counter[26])
def __init__(self):
self.write_port = LiteDRAMWritePort(aw=32, dw=32)
self.read_port = LiteDRAMReadPort(aw=32, dw=32)
self.submodules.generator = LiteDRAMBISTGenerator(self.write_port,
random=True)
self.submodules.checker = LiteDRAMBISTChecker(self.read_port,
random=True)
def __init__(self):
# phy
sdram_module = SimModule(1000, "1:1")
phy_settings = PhySettings(memtype="SDR",
dfi_databits=1 * 16,
nphases=1,
rdphase=0,
wrphase=0,
rdcmdphase=0,
wrcmdphase=0,
cl=2,
read_latency=4,
write_latency=0)
self.submodules.sdrphy = SDRAMPHYModel(sdram_module,
phy_settings,
we_granularity=0)
# controller
self.submodules.controller = LiteDRAMController(
phy_settings,
sdram_module.geom_settings, sdram_module.timing_settings,
ControllerSettings(with_refresh=False))
self.comb += self.controller.dfi.connect(self.sdrphy.dfi)
self.submodules.crossbar = LiteDRAMCrossbar(self.controller.interface,
self.controller.nrowbits)
# write port
write_user_port = self.crossbar.get_port("write", cd="write")
read_user_port = self.crossbar.get_port("read", cd="read")
# generator / checker
self.submodules.generator = LiteDRAMBISTGenerator(write_user_port)
self.submodules.checker = LiteDRAMBISTChecker(read_user_port)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.generator = LiteDRAMBISTGenerator(
self.sdram.crossbar.get_port(mode="write"))
#self.submodules.checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port(mode="read", dw=16)) #, cd="hdmi_out1_pix"))
self.submodules.checker = LiteDRAMBISTChecker(
self.sdram.crossbar.get_port(mode="read")) #, cd="hdmi_out1_pix"))
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.generator = LiteDRAMBISTGenerator(
self.sdram.crossbar.get_port(mode="write"),
)
#self.submodules.checker = LiteDRAMBISTChecker(
# self.sdram.crossbar.get_port(mode="read", data_width=16),
# clock_domain="hdmi_out1_pix",
#)
self.submodules.checker = LiteDRAMBISTChecker(
self.sdram.crossbar.get_port(mode="read"),
# cd="hdmi_out1_pix"),
)
def __init__(self, platform, **kwargs):
kwargs['cpu_type'] = None
clk_freq = 100 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="NeTV2 LiteX Base SoC",
with_uart=False,
**kwargs)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
self.clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 8)
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# sdram bist
ddr_generator_port = self.sdram.crossbar.get_port(mode="write")
self.submodules.ddr_generator = LiteDRAMBISTGenerator(
ddr_generator_port)
ddr_checker_port = self.sdram.crossbar.get_port(mode="read")
self.submodules.ddr_checker = LiteDRAMBISTChecker(ddr_checker_port)
# led blink
counter = Signal(32)
self.sync += counter.eq(counter + 1)
self.comb += platform.request("user_led", 0).eq(counter[26])
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.generator = LiteDRAMBISTGenerator(
self.sdram.crossbar.get_port(
mode="write",
data_width=32,
),
random=False,
)
self.submodules.checker = LiteDRAMBISTChecker(
self.sdram.crossbar.get_port(
mode="read",
data_width=32,
reverse=True,
),
random=False,
)
self.submodules.checker_scope = LiteDRAMBISTCheckerScope(self.checker)
analyzer_signals = self.checker_scope.signals()
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024)
def __init__(self, **kwargs):
EthernetSoC.__init__(self, **kwargs)
self.submodules.sdram_generator = LiteDRAMBISTGenerator(
self.sdram.crossbar.get_port())
self.submodules.sdram_checker = LiteDRAMBISTChecker(
self.sdram.crossbar.get_port())
def __init__(self, platform,
with_sdram_bist=True, bist_async=True, bist_random=False):
clk_freq = 100*1000000
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_type=None,
l2_size=32,
csr_data_width=32,
with_uart=False,
with_timer=False)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random)
# uart
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# logic analyzer
analyzer_signals = [Signal(2)]
if False:
analyzer_signals = [
generator_user_port.cmd.valid,
generator_user_port.cmd.ready,
generator_user_port.cmd.we,
generator_user_port.cmd.adr,
generator_user_port.wdata.valid,
generator_user_port.wdata.ready,
generator_user_port.wdata.we,
self.generator.start.re,
self.checker.start.re
]
if False:
gen_data = Signal(32)
read_data = Signal(32)
self.comb += [
gen_data.eq(self.checker.core.gen.o),
read_data.eq(checker_user_port.rdata.data)
]
analyzer_signals = [
checker_user_port.cmd.valid,
checker_user_port.cmd.ready,
checker_user_port.cmd.we,
checker_user_port.cmd.adr,
checker_user_port.rdata.valid,
checker_user_port.rdata.ready,
self.generator.start.re,
self.checker.start.re,
gen_data,
read_data,
self.checker.core.errors
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self,
platform,
with_sdram_bist=True,
bist_async=True,
bist_random=True,
spiflash="spiflash_1x",
**kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
with_uart=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
uart_interfaces = [RS232PHYInterface() for i in range(2)]
self.submodules.uart = UART(uart_interfaces[0])
self.submodules.bridge = WishboneStreamingBridge(
uart_interfaces[1], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
self.submodules.uart_phy = RS232PHY(platform.request("serial"),
self.clk_freq, 115200)
self.submodules.uart_multiplexer = UARTMultiplexer(
uart_interfaces, self.uart_phy)
self.comb += self.uart_multiplexer.sel.eq(
platform.request("user_sw", 0))
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(100e6))
self.submodules.leds = led.ClassicLed(
Cat(platform.request("user_led", i) for i in range(4)))
self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 3)
self.add_constant("A7DDRPHY_DELAY", 14)
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(
self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(cmd_buffer_depth=8))
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(
mode="write", cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(
generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(
mode="read", cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port,
random=bist_random)
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
16 * 1024 * 1024)
def __init__(self, platform, ddram="ddram_32", with_cpu=False):
clk_freq = int(125e6)
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_type="lm32" if with_cpu else None,
integrated_rom_size=0x8000 if with_cpu else 0,
integrated_sram_size=0x8000 if with_cpu else 0,
csr_data_width=8 if with_cpu else 32,
l2_size=128,
with_uart=with_cpu, uart_stub=False,
ident="Sayma AMC SDRAM Test Design " + _build_version(),
with_timer=with_cpu
)
self.submodules.crg = _CRG(platform)
if not with_cpu:
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"),
clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.crg.cd_sys.clk.attr.add("keep")
platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
# firmware
firmware_ram_size = 0x10000
firmware_filename = "firmware/firmware.bin"
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
# sdram
self.submodules.ddrphy = kusddrphy.KUSDDRPHY(platform.request(ddram))
sdram_module = MT41J256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# sdram bist
if not with_cpu:
generator_user_port = self.sdram.crossbar.get_port(mode="write")
self.submodules.generator = LiteDRAMBISTGenerator(
generator_user_port, random=True)
checker_user_port = self.sdram.crossbar.get_port(mode="read")
self.submodules.checker = LiteDRAMBISTChecker(
checker_user_port, random=True)
# leds
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += [
platform.request("user_led", 0).eq(led_counter[26]),
platform.request("user_led", 1).eq(led_counter[27]),
platform.request("user_led", 2).eq(led_counter[28]),
platform.request("user_led", 3).eq(led_counter[29])
]
# analyzer
if not with_cpu:
dfi_phase_groups = []
for i in range(4):
dfi_phase_group = [
self.ddrphy.dfi.phases[i].address,
self.ddrphy.dfi.phases[i].bank,
self.ddrphy.dfi.phases[i].ras_n,
self.ddrphy.dfi.phases[i].cas_n,
self.ddrphy.dfi.phases[i].we_n,
self.ddrphy.dfi.phases[i].cs_n,
self.ddrphy.dfi.phases[i].cke,
self.ddrphy.dfi.phases[i].odt,
self.ddrphy.dfi.phases[i].reset_n,
self.ddrphy.dfi.phases[i].wrdata_en,
self.ddrphy.dfi.phases[i].wrdata_mask,
self.ddrphy.dfi.phases[i].wrdata,
self.ddrphy.dfi.phases[i].rddata,
self.ddrphy.dfi.phases[i].rddata_valid
]
dfi_phase_groups.append(dfi_phase_group)
analyzer_signals = {
0 : dfi_phase_groups[0],
1 : dfi_phase_groups[1],
2 : dfi_phase_groups[2],
3 : dfi_phase_groups[3]
}
if not with_cpu:
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 64)
def __init__(self,
platform,
with_sdram_bist=True, bist_async=True, bist_random=True,
spiflash="spiflash_1x",
**kwargs):
clk_freq = 100*1000000
SoCSDRAM.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.submodules.leds = led.ClassicLed(Cat(platform.request("user_led", i) for i in range(4)))
self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 6)
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(cmd_buffer_depth=8))
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(mode="write", cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(mode="read", cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random)
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base, 16*1024*1024)
# uart mux
uart_sel = platform.request("user_sw", 0)
self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200)
uart_phys = {
"cpu": UARTVirtualPhy(),
"bridge": UARTVirtualPhy()
}
self.comb += [
If(uart_sel,
self.uart_phy.source.connect(uart_phys["bridge"].source),
uart_phys["bridge"].sink.connect(self.uart_phy.sink),
uart_phys["cpu"].source.ready.eq(1) # avoid stalling cpu
).Else(
self.uart_phy.source.connect(uart_phys["cpu"].source),
uart_phys["cpu"].sink.connect(self.uart_phy.sink),
uart_phys["bridge"].source.ready.eq(1) # avoid stalling bridge
)
]
# uart cpu
self.submodules.uart = UART(uart_phys["cpu"])
# uart bridge
self.submodules.bridge = WishboneStreamingBridge(uart_phys["bridge"], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)