def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): platform = nexys_video.Platform() # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=integrated_rom_size, integrated_sram_size=0x8000, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT41K256M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size']=0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size']=0x8000 clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) uart_interfaces = [RS232PHYInterface() for i in range(2)] self.submodules.uart = UART(uart_interfaces[0]) self.submodules.bridge = WishboneStreamingBridge(uart_interfaces[1], self.clk_freq) self.add_wb_master(self.bridge.wishbone) self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200) self.submodules.uart_multiplexer = RS232PHYMultiplexer(uart_interfaces, self.uart_phy) self.comb += self.uart_multiplexer.sel.eq(platform.request("user_sw", 0)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.oled = oled.OLED(platform.request("oled")) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # spi flash spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=2) self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region( "spiflash", self.mem_map["spiflash"], 16*1024*1024) self.add_interrupt("uart")
def __init__(self, platform, **kwargs): clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, cpu_type=None, l2_size=32, with_uart=False, with_timer=False) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # uart self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy)
def __init__(self, platform, **kwargs): clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() self.submodules.oled = oled.OLED(platform.request("oled")) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True))
def __init__(self, device="85F", sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, **kwargs): platform = ecpix5.Platform(device=device, toolchain="trellis") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECPIX-5", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), rx_delay=0e-9) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- leds_pads = [] for i in range(4): rgb_led_pads = platform.request("rgb_led", i) self.comb += [getattr(rgb_led_pads, n).eq(1) for n in "gb"] # Disable Green/Blue Leds. leds_pads += [getattr(rgb_led_pads, n) for n in "r"] self.submodules.leds = LedChaser(pads=Cat(leds_pads), sys_clk_freq=sys_clk_freq)
def __init__(self, **kwargs): platform = nexys_video.Platform() SoCSDRAM.__init__(self, platform, clk_freq=100*1000000, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs): platform = ecpix5.Platform(toolchain="trellis") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECPIX-5", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), rx_delay=0e-9) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # Leds (Disable...) ------------------------------------------------------------------------ for i in range(4): rgb_led_pads = platform.request("rgb_led", i) for c in "rgb": self.comb += getattr(rgb_led_pads, c).eq(1)
def __init__(self, platform, with_analyzer=False, with_loopback=False): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, cpu_type=None, l2_size=32, csr_data_width=32, csr_address_width=15, # required for flash spi integrated_rom_size=0, integrated_sram_size=0x8000, with_uart=False, ident="USB2Sniffer design", with_timer=False ) self.submodules.crg = _CRG(platform) # flash spi self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(clk_freq/25e6)) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # sdram fifo depth = 32 * 1024 * 1024 self.submodules.dramfifo = ResetInserter()(LiteDRAMFIFO([("data", 32)], depth, 0, self.sdram.crossbar, preserve_first_last=False)) self.submodules.hugefifo = ResetInserter()(stream.SyncFIFO([("data", 32)], 512)) # debug wishbone self.add_cpu(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=3e6)) self.add_wb_master(self.cpu.wishbone) # usb phy usb_pads = platform.request("usb_fifo") self.submodules.usb_phy = FT601Sync(usb_pads, dw=32, timeout=1024) if with_loopback: self.submodules.usb_loopback_fifo = stream.SyncFIFO(phy_description(32), 2048) self.comb += [ self.usb_phy.source.connect(self.usb_loopback_fifo.sink), self.usb_loopback_fifo.source.connect(self.usb_phy.sink) ] else: # usb core self.submodules.usb_core = USBCore(self.usb_phy, clk_freq) # usb <--> wishbone self.submodules.etherbone = Etherbone(self.usb_core, self.usb_map["wishbone"]) self.add_wb_master(self.etherbone.master.bus) # ulpi switch ulpi_sw = platform.request("ulpi_sw") self.submodules.ulpi_sw_oe_n = GPIOOut(ulpi_sw.oe_n) self.submodules.ulpi_sw_s = GPIOOut(ulpi_sw.s) # ulpi 0 self.submodules.ulpi_phy0 = ULPIPHY(platform.request("ulpi", 0), cd="ulpi0") self.submodules.ulpi_core0 = ULPICore(self.ulpi_phy0) # packer0 self.submodules.overflow0 = OverflowMeter(ulpi_cmd_description(8, 1)) self.submodules.iticore0 = ITICore() self.submodules.fifo0 = ResetInserter()(stream.SyncFIFO([("data", 40), ("len", 2)], 16)) self.submodules.conv40320 = Conv4032() # ulpi 1 self.submodules.ulpi_phy1 = ULPIPHY(platform.request("ulpi", 1), cd="ulpi1") self.submodules.ulpi_core1 = ULPICore(self.ulpi_phy1) # usb <--> ulpi0 self.submodules.wrapcore0 = WrapCore(self.usb_core, self.usb_map["ulpi0"]) self.comb += [ self.ulpi_core0.source.connect(self.overflow0.sink), self.overflow0.source.connect(self.iticore0.sink), self.iticore0.source.connect(self.fifo0.sink), self.fifo0.source.connect(self.conv40320.sink), self.conv40320.source.connect(self.hugefifo.sink), self.hugefifo.source.connect(self.dramfifo.sink), self.dramfifo.source.connect(self.wrapcore0.sink), ] # reset manager self.rst_manager = ResetManager([self.iticore0, self.fifo0, self.conv40320, self.hugefifo, self.dramfifo, self.wrapcore0]) # leds led0 = platform.request("rgb_led", 0) self.submodules.blinker0 = BlinkerRGB(led0, self.etherbone.packet.tx.source.valid, 0, self.etherbone.packet.rx.sink.valid) led1 = platform.request("rgb_led", 1) self.submodules.blinker1 = BlinkerRGB(led1, self.ulpi_core0.source.valid, 0, self.wrapcore0.sender.source.valid) # timing constraints self.crg.cd_sys.clk.attr.add("keep") self.crg.cd_usb.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.crg.cd_usb.clk, 10.0) if with_analyzer: analyzer_signals = [ self.ulpi_core0.source.valid, self.ulpi_core0.source.ready, self.ulpi_core0.source.data, self.iticore0.source.valid, self.iticore0.source.ready, self.iticore0.source.data, self.fifo.source.valid, self.fifo.source.ready, self.fifo.source.data, self.wrapcore0.sender.source.valid, self.wrapcore0.sender.source.ready, self.wrapcore0.sender.source.data, ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024, clock_domain="sys")
def __init__(self, revision="1.0", device="25F", sys_clk_freq=int(60e6), toolchain="trellis", with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_spi_flash=False, with_led_chaser=True, **kwargs): platform = butterstick.Platform(revision=revision, device=device, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "crossover" SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ButterStick", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:2"), l2_cache_size=kwargs.get("l2_size", 8192)) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import W25Q128JV from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=False) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.comb += platform.request("user_led_color").eq(0b010) # Blue. self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, platform, with_sdram_bist=True, bist_async=True, bist_random=False, **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, cpu_type=None, l2_size=32, csr_data_width=32, with_uart=False, with_timer=False) self.submodules.crg = CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # sdram bist if with_sdram_bist: generator_user_port = self.sdram.crossbar.get_port( cd="clk50" if bist_async else "sys") self.submodules.generator = LiteDRAMBISTGenerator( generator_user_port, random=bist_random) checker_user_port = self.sdram.crossbar.get_port( cd="clk50" if bist_async else "sys") self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random) # uart self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) # logic analyzer analyzer_signals = [Signal(2)] if False: analyzer_signals = [ generator_user_port.cmd.valid, generator_user_port.cmd.ready, generator_user_port.cmd.we, generator_user_port.cmd.adr, generator_user_port.wdata.valid, generator_user_port.wdata.ready, generator_user_port.wdata.we, self.generator.start.re, self.checker.start.re ] if False: gen_data = Signal(32) read_data = Signal(32) self.comb += [ gen_data.eq(self.checker.core.gen.o), read_data.eq(checker_user_port.rdata.data) ] analyzer_signals = [ checker_user_port.cmd.valid, checker_user_port.cmd.ready, checker_user_port.cmd.we, checker_user_port.cmd.adr, checker_user_port.rdata.valid, checker_user_port.rdata.ready, self.generator.start.re, self.checker.start.re, gen_data, read_data, self.checker.core.errors ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6))
def __init__(self, platform, with_cpu=False, with_analyzer=True, with_loopback=False): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, cpu_type="lm32" if with_cpu else None, integrated_rom_size=0x8000 if with_cpu else 0, integrated_sram_size=0x8000, with_uart=with_cpu, ident="PCIe Injector example design", with_timer=with_cpu) self.submodules.crg = _CRG(platform) if not with_cpu: # use serial as wishbone bridge when no cpu self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=3000000)) self.add_wb_master(self.cpu_or_bridge.wishbone) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # pcie endpoint self.submodules.pciephy = S7PCIEPHY(platform, platform.request("pcie_x1"), cd="sys") # usb core usb_pads = platform.request("usb_fifo") # self.submodules.usb_phy = FT245PHYSynchronous(usb_pads, clk_freq, fifo_depth=16) self.submodules.usb_phy = FT601Sync(usb_pads, dw=32, timeout=1024) if with_loopback: self.submodules.usb_loopback_fifo = stream.SyncFIFO( phy_description(32), 2048) self.comb += [ self.usb_phy.source.connect(self.usb_loopback_fifo.sink), self.usb_loopback_fifo.source.connect(self.usb_phy.sink) ] else: self.submodules.usb_core = USBCore(self.usb_phy, clk_freq) # usb <--> wishbone self.submodules.etherbone = Etherbone(self.usb_core, self.usb_map["wishbone"]) self.add_wb_master(self.etherbone.master.bus) # usb <--> tlp self.submodules.tlp = TLP(self.usb_core, self.usb_map["tlp"]) self.comb += [ self.pciephy.source.connect(self.tlp.sender.sink), self.tlp.receiver.source.connect(self.pciephy.sink) ] # wishbone --> msi self.submodules.msi = MSI() self.comb += self.msi.source.connect(self.pciephy.msi) # led blink usb_counter = Signal(32) self.sync.usb += usb_counter.eq(usb_counter + 1) self.comb += platform.request("user_led", 0).eq(usb_counter[26]) pcie_counter = Signal(32) self.sync.pcie += pcie_counter.eq(pcie_counter + 1) self.comb += platform.request("user_led", 1).eq(pcie_counter[26]) # timing constraints self.crg.cd_sys.clk.attr.add("keep") self.crg.cd_usb.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.crg.cd_usb.clk, 10.0) self.platform.add_period_constraint( self.platform.lookup_request("pcie_x1").clk_p, 10.0) if with_analyzer: analyzer_signals = [ self.pciephy.sink.valid, self.pciephy.sink.ready, self.pciephy.sink.last, self.pciephy.sink.dat, self.pciephy.sink.be, self.pciephy.source.valid, self.pciephy.source.ready, self.pciephy.source.last, self.pciephy.source.dat, self.pciephy.source.be ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024, cd="sys")
def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Acorn CLE 215+", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = DNA() self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = XADC() self.add_csr("xadc") # ICAP ------------------------------------------------------------------------------------- self.submodules.icap = ICAP(platform) self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("icap") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41K256M16(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # PCIe ------------------------------------------------------------------------------------- # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 64, bar0_size = 0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") self.comb += platform.request("pcie_clkreq_n").eq(0) # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, base_address = self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = True, buffering_depth=1024, with_loopback = True) self.add_csr("pcie_dma0") # DMA1 self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = True, buffering_depth=1024, with_loopback = True) self.add_csr("pcie_dma1") self.add_constant("DMA_CHANNELS", 2) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_sata=False, **kwargs): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Nexys Video", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # AB09-FMCRAID / https://www.dgway.com/AB09-FMCRAID_E.html ("fmc2sata", 0, Subsignal("clk_p", Pins("LPC:GBTCLK0_M2C_P")), Subsignal("clk_n", Pins("LPC:GBTCLK0_M2C_N")), Subsignal("tx_p", Pins("LPC:DP0_C2M_P")), Subsignal("tx_n", Pins("LPC:DP0_C2M_N")), Subsignal("rx_p", Pins("LPC:DP0_M2C_P")), Subsignal("rx_n", Pins("LPC:DP0_M2C_N"))), ] platform.add_extension(_sata_io) # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, pads=platform.request("fmc2sata"), gen="gen2", clk_freq=sys_clk_freq, data_width=16) self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, cpu_variant="1c", **kwargs): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- kwargs["integrated_rom_size"] = 0x10000 SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_cls=VexRiscvSMP, cpu_variant=cpu_variant, **kwargs) # PLIC ------------------------------------------------------------------------------------ self.bus.add_slave("plic", self.cpu.plicbus, region=SoCRegion(origin=0xf0C00000, size=0x400000, cached=False)) # CLINT ------------------------------------------------------------------------------------ self.bus.add_slave("clint", self.cpu.cbus, region=SoCRegion(origin=0xf0010000, size=0x10000, cached=False)) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True, controller_settings=ControllerSettings( cmd_buffer_buffered=False, with_auto_precharge=False)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # JTAG --------------------------------------------------------------------------------- self.submodules.jtag = S7JTAG() self.comb += self.cpu.jtag_clk.eq(self.jtag.tck) self.comb += self.cpu.jtag_enable.eq(1) self.comb += self.cpu.jtag_capture.eq(self.jtag.capture) self.comb += self.cpu.jtag_shift.eq(self.jtag.shift) self.comb += self.cpu.jtag_update.eq(self.jtag.update) self.comb += self.cpu.jtag_reset.eq(self.jtag.reset) self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi) self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): if kwargs.get('cpu_type', None) == 'mor1kx': dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) sys_clk_freq = int(100e6) # disable uart kwargs['with_uart'] = False # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if True: sdram_module = MT41K256M16(sys_clk_freq, "1:4") self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype=sdram_module.memtype, nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # Extended UART ---------------------------------------------------------------------------- uart_interfaces = [RS232PHYInterface() for i in range(2)] self.submodules.uart = UART(uart_interfaces[0]) self.submodules.bridge = Stream2Wishbone(uart_interfaces[1], sys_clk_freq) self.add_wb_master(self.bridge.wishbone) self.add_csr("uart") self.add_interrupt("uart") self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200) self.submodules.uart_multiplexer = RS232PHYMultiplexer( uart_interfaces, self.uart_phy) self.comb += self.uart_multiplexer.sel.eq( platform.request("user_sw", 0)) self.add_csr("uart_phy") # Basic peripherals ------------------------------------------------------------------------ self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") # self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) # self.add_csr("cas") self.submodules.oled = oled.OLED(platform.request("oled")) self.add_csr("oled") # Add debug interface if the CPU has one --------------------------------------------------- if hasattr(self.cpu, "debug_bus"): self.register_mem(name="vexriscv_debug", address=0xf00f0000, interface=self.cpu.debug_bus, size=0x100) # Memory mapped SPI Flash ------------------------------------------------------------------ spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=platform.spiflash_clock_div, endianness=self.cpu.endianness) self.add_csr("spiflash") self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size) self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus, platform.spiflash_total_size) self.add_memory_region("spiflash", self.mem_map["spiflash"], platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_led_chaser=True, with_sata=False, sata_gen="gen2", vadj="1.2V", with_video_terminal=False, with_video_framebuffer=False, **kwargs): platform = nexys_video.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Nexys Video", **kwargs) # CRG -------------------------------------------------------------------------------------- with_video_pll = (with_video_terminal or with_video_framebuffer) self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain, with_video_pll=with_video_pll) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", phy = self.ddrphy, module = MT41K256M16(sys_clk_freq, "1:4"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) self.add_ethernet(phy=self.ethphy) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # AB09-FMCRAID / https://www.dgway.com/AB09-FMCRAID_E.html ("fmc2sata", 0, Subsignal("clk_p", Pins("LPC:GBTCLK0_M2C_P")), Subsignal("clk_n", Pins("LPC:GBTCLK0_M2C_N")), Subsignal("tx_p", Pins("LPC:DP0_C2M_P")), Subsignal("tx_n", Pins("LPC:DP0_C2M_N")), Subsignal("rx_p", Pins("LPC:DP0_M2C_P")), Subsignal("rx_n", Pins("LPC:DP0_M2C_N")) ), ] platform.add_extension(_sata_io) # PHY self.submodules.sata_phy = LiteSATAPHY(platform.device, pads = platform.request("fmc2sata"), gen = sata_gen, clk_freq = sys_clk_freq, data_width = 16) # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) # VADJ ------------------------------------------------------------------------------------- vadj_map = {"1.2V": 0b00, "1.8V": 0b01, "2.5V": 0b10, "3.3V": 0b11} platform.request_all("vadj").eq(vadj_map[vadj])
def __init__(self, device="85F", sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, with_video_terminal=False, with_video_framebuffer=False, with_led_chaser=True, **kwargs): platform = ecpix5.Platform(device=device, toolchain="trellis") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECPIX-5", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:2"), l2_cache_size=kwargs.get("l2_size", 8192)) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), rx_delay=0e-9) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # HDMI ------------------------------------------------------------------------------------- if with_video_terminal or with_video_framebuffer: # PHY + IT6613 I2C initialization. hdmi_pads = platform.request("hdmi") self.submodules.videophy = VideoDVIPHY(hdmi_pads, clock_domain="init") self.submodules.videoi2c = I2CMaster(hdmi_pads) # I2C initialization adapted from https://github.com/ultraembedded/ecpix-5 # Copyright (c) 2020 https://github.com/ultraembedded # Adapted from C to Python. REG_TX_SW_RST = 0x04 B_ENTEST = (1 << 7) B_REF_RST = (1 << 5) B_AREF_RST = (1 << 4) B_VID_RST = (1 << 3) B_AUD_RST = (1 << 2) B_HDMI_RST = (1 << 1) B_HDCP_RST = (1 << 0) REG_TX_AFE_DRV_CTRL = 0x61 B_AFE_DRV_PWD = (1 << 5) B_AFE_DRV_RST = (1 << 4) B_AFE_DRV_PDRXDET = (1 << 2) B_AFE_DRV_TERMON = (1 << 1) B_AFE_DRV_ENCAL = (1 << 0) REG_TX_AFE_XP_CTRL = 0x62 B_AFE_XP_GAINBIT = (1 << 7) B_AFE_XP_PWDPLL = (1 << 6) B_AFE_XP_ENI = (1 << 5) B_AFE_XP_ER0 = (1 << 4) B_AFE_XP_RESETB = (1 << 3) B_AFE_XP_PWDI = (1 << 2) B_AFE_XP_DEI = (1 << 1) B_AFE_XP_DER = (1 << 0) REG_TX_AFE_ISW_CTRL = 0x63 B_AFE_RTERM_SEL = (1 << 7) B_AFE_IP_BYPASS = (1 << 6) M_AFE_DRV_ISW = (7 << 3) O_AFE_DRV_ISW = 3 B_AFE_DRV_ISWK = 7 REG_TX_AFE_IP_CTRL = 0x64 B_AFE_IP_GAINBIT = (1 << 7) B_AFE_IP_PWDPLL = (1 << 6) M_AFE_IP_CKSEL = (3 << 4) O_AFE_IP_CKSEL = 4 B_AFE_IP_ER0 = (1 << 3) B_AFE_IP_RESETB = (1 << 2) B_AFE_IP_ENC = (1 << 1) B_AFE_IP_EC1 = (1 << 0) REG_TX_HDMI_MODE = 0xC0 B_TX_HDMI_MODE = 1 B_TX_DVI_MODE = 0 REG_TX_GCP = 0xC1 B_CLR_AVMUTE = 0 B_SET_AVMUTE = 1 B_TX_SETAVMUTE = (1 << 0) B_BLUE_SCR_MUTE = (1 << 1) B_NODEF_PHASE = (1 << 2) B_PHASE_RESYNC = (1 << 3) self.videoi2c.add_init( addr=0x4c, init=[ # Reset. (REG_TX_SW_RST, B_REF_RST | B_VID_RST | B_AUD_RST | B_AREF_RST | B_HDCP_RST), (REG_TX_SW_RST, 0), # Select DVI Mode. (REG_TX_HDMI_MODE, B_TX_DVI_MODE), # Configure Clks. (REG_TX_SW_RST, B_AUD_RST | B_AREF_RST | B_HDCP_RST), (REG_TX_AFE_DRV_CTRL, B_AFE_DRV_RST), (REG_TX_AFE_XP_CTRL, 0x18), (REG_TX_AFE_ISW_CTRL, 0x10), (REG_TX_AFE_IP_CTRL, 0x0C), # Enable Clks. (REG_TX_AFE_DRV_CTRL, 0), # Enable Video. (REG_TX_GCP, 0), ]) # Video Terminal/Framebuffer. if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="init") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="init") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: leds_pads = [] for i in range(4): rgb_led_pads = platform.request("rgb_led", i) self.comb += [getattr(rgb_led_pads, n).eq(1) for n in "gb"] # Disable Green/Blue Leds. leds_pads += [getattr(rgb_led_pads, n) for n in "r"] self.submodules.leds = LedChaser(pads=Cat(leds_pads), sys_clk_freq=sys_clk_freq)