def __init__(self, **kwargs):
sys_clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
platform = pipistrello.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
# LPDDR SDRAM ------------------------------------------------------------------------------
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
memtype="LPDDR",
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.add_csr("ddrphy")
sdram_module = MT46H32M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self, with_led_chaser=True, **kwargs):
sys_clk_freq = (83 + Fraction(1, 3))*1000*1000
platform = pipistrello.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Pipistrello",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
# LPDDR SDRAM ------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
memtype = "LPDDR",
rd_bitslip = 1,
wr_bitslip = 3,
dqs_ddr_alignment = "C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT46H32M16(sys_clk_freq, "1:2"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
platform = pipistrello.Platform()
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
bios_size = 0x8000
# sdram
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.add_csr("ddrphy")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
clk_freq = (31 + Fraction(1, 4)) * 1000 * 1000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
# sdram
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=2,
wr_bitslip=3,
dqs_ddr_alignment="C1")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, **kwargs):
sys_clk_freq = (83 + Fraction(1, 3))*1000*1000
platform = pipistrello.Platform()
# SoCCore -----------------------------------------------------------------_----------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
# LPDDR SDRAM ------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
memtype = "LPDDR",
rd_bitslip = 1,
wr_bitslip = 3,
dqs_ddr_alignment = "C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT46H32M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
def __init__(self, platform, **kwargs):
# Need a larger integrated ROM to fit the BIOS with TFTP support.
dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
clk_freq = (31 + Fraction(1, 4))*1000*1000
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
# sdram
if not self.integrated_main_ram_size:
sdram_module = MT46H32M16(clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=2,
wr_bitslip=3,
dqs_ddr_alignment="C1"
)
self.add_csr("ddrphy")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True)
)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
cpu_reset_address = self.mem_map["spiflash"] + platform.gateware_size
clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
SoCSDRAM.__init__(
self,
platform,
clk_freq,
#integrated_rom_size=0x8000,
integrated_rom_size=None,
integrated_sram_size=0x4000,
uart_baudrate=(19200, 115200)[int(os.environ.get('JIMMO', '0'))],
cpu_reset_address=cpu_reset_address,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# spi flash
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom", cpu_reset_address, bios_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
# sdram
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
kwargs['uart_baudrate'] = 230400
sys_clk_freq = int(75 * 1000 * 1000)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
# Basic peripherals ------------------------------------------------------------------------
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Memory mapped SPI Flash ------------------------------------------------------------------
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
# SDRAM ------------------------------------------------------------------------------------
sdram_module = MT47H32M16(self.sys_clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, with_ethernet=True, with_etherbone=False, eth_phy=0, **kwargs):
sys_clk_freq = int(75e6)
platform = atlys.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Atlys",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
memtype = "DDR2",
rd_bitslip = 0,
wr_bitslip = 4,
dqs_ddr_alignment = "C0")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT47H64M16(sys_clk_freq, "1:2"),
l2_cache_size = kwargs.get("l2_size", 8192),
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
from liteeth.phy import LiteEthPHYGMIIMII
self.submodules.ethphy = LiteEthPHYGMIIMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy),
clk_freq = int(self.sys_clk_freq))
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_platform_command("""
NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE;
NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE;
""",
eth_clocks_rx=platform.lookup_request("eth_clocks").rx,
eth_clocks_tx=platform.lookup_request("eth_clocks").tx,
)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
sys_clk_freq = (31 + Fraction(1, 4)) * 1000 * 1000
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if True:
sdram_module = MT46H32M16(sys_clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
memtype=sdram_module.memtype,
rd_bitslip=2,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.add_csr("ddrphy")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
# Basic peripherals ------------------------------------------------------------------------
# info module
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
# control and status module
#self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Add debug interface if the CPU has one ---------------------------------------------------
if hasattr(self.cpu, "debug_bus"):
self.register_mem(name="vexriscv_debug",
address=0xf00f0000,
interface=self.cpu.debug_bus,
size=0x100)
# Memory mapped SPI Flash ------------------------------------------------------------------
# TODO: Add SPI Flash support here.
# Support for soft-emulation for full Linux support ----------------------------------------
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
def __init__(self, platform, **kwargs):
clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
self.submodules.info = info.Info(platform, "pipi",
self.__class__.__name__[:8])
# self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
# self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("opsis_eeprom"))
self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200)
self.suart.add_uart_pads(platform.request('fx2_serial'))
self.submodules.uart = self.suart.uart
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash4x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
# sdram
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
clk_freq = 75 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
with_uart=True,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
self.submodules.info = info.Info(platform, "atlys",
self.__class__.__name__[:8])
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash4x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
#self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# sdram
sdram_module = P3R1GE4JGF(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
if kwargs.get('cpu_type', None) == 'mor1kx':
dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
else:
dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
sys_clk_freq = (31 + Fraction(1, 4)) * 1000 * 1000
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if True:
sdram_module = MT46H32M16(sys_clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
memtype=sdram_module.memtype,
rd_bitslip=2,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.add_csr("ddrphy")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
# Basic peripherals ------------------------------------------------------------------------
# info module
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
# control and status module
#self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Add debug interface if the CPU has one ---------------------------------------------------
if hasattr(self.cpu, "debug_bus"):
self.register_mem(name="vexriscv_debug",
address=0xf00f0000,
interface=self.cpu.debug_bus,
size=0x100)
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x4000
clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash4x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
# sdram
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
clk_freq = int(50e6)
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
gmii_rst_n = platform.request("gmii_rst_n")
self.comb += [gmii_rst_n.eq(1)]
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
# sdram
sdram_module = MT47H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram_b"),
sdram_module.memtype,
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size']=0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size']=0x8000
clk_freq = (31 + Fraction(1, 4))*1000*1000
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size)
# sdram
if not self.integrated_main_ram_size:
sdram_module = MT46H32M16(clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=2,
wr_bitslip=3,
dqs_ddr_alignment="C1"
)
self.add_csr("ddrphy")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True)
)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
# disable ROM, it'll be added later
kwargs['integrated_rom_size'] = 0x0
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
if os.environ.get('JIMMO', '0') == '0':
kwargs['uart_baudrate'] = 19200
else:
kwargs['uart_baudrate'] = 115200
sys_clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if True:
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
memtype=sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.add_csr("ddrphy")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
# Basic peripherals ------------------------------------------------------------------------
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Add debug interface if the CPU has one ---------------------------------------------------
if hasattr(self.cpu, "debug_bus"):
self.register_mem(name="vexriscv_debug",
address=0xf00f0000,
interface=self.cpu.debug_bus,
size=0x100)
# Memory mapped SPI Flash ------------------------------------------------------------------
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus,
platform.spiflash_total_size)
self.add_memory_region("spiflash", self.mem_map["spiflash"],
platform.spiflash_total_size)
if kwargs.get('cpu_type', None) == "mor1kx":
bios_size = 0x10000
else:
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom",
kwargs['cpu_reset_address'],
bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
define_flash_constants(self)
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = None
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x4000
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
#kwargs['uart_baudrate']=115200
clk_freq = (15 + Fraction(5, 8)) * 1000 * 1000 #15625000
SoCSDRAM.__init__(self, platform, clk_freq,
**kwargs) #with_uart=False,
self.submodules.crg = _CRG(platform, clk_freq)
# spi flash
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
#self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
# self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
# self.submodules.uart = uart.UART(self.uart_phy)
# self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), self.clk_freq, baudrate=115200)
# self.add_wb_master(self.bridge.wishbone)
# # Litescope for analyzing the BIST output
# # --------------------
# self.submodules.io = LiteScopeIO(8)
# for i in range(8):
# try:
# self.comb += platform.request("user_led", i).eq(self.io.output[i])
# except:
# pass
# analyzer_signals = [
# self.spiflash.bus,
# # self.spiflash.cs_n,
# # self.spiflash.clk,
# # self.spiflash.dq_oe,
# # self.spiflash.dqi,
# # self.spiflash.sr,
# ]
# self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024)
# def do_exit(self, vns, filename="test/analyzer.csv"):
# self.analyzer.export_csv(vns, filename)
# sdram
sdram_module = MT47H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=2,
wr_bitslip=3,
dqs_ddr_alignment="C1")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
sys_clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if True:
sdram_module = MT46H32M16(sys_clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
memtype=sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.add_csr("ddrphy")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
# Basic peripherals ------------------------------------------------------------------------
# info module
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
# control and status module
#self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Add debug interface if the CPU has one ---------------------------------------------------
if hasattr(self.cpu, "debug_bus"):
self.register_mem(name="vexriscv_debug",
address=0xf00f0000,
interface=self.cpu.debug_bus,
size=0x100)
# Memory mapped SPI Flash ------------------------------------------------------------------
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash4x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus,
platform.spiflash_total_size)
self.add_memory_region("spiflash", self.mem_map["spiflash"],
platform.spiflash_total_size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
define_flash_constants(self)
# Support for soft-emulation for full Linux support ----------------------------------------
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
def __init__(self, platform, **kwargs):
if kwargs.get('cpu_type', None) == 'mor1kx':
dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
else:
dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
sys_clk_freq = int(50e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if True:
sdram_module = MT47H32M16(sys_clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram_b"),
memtype = sdram_module.memtype,
rd_bitslip = 0,
wr_bitslip = 4,
dqs_ddr_alignment="C0")
self.add_csr("ddrphy")
controller_settings = ControllerSettings(
with_bandwidth=True)
self.register_sdram(
self.ddrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
# Basic peripherals ------------------------------------------------------------------------
# info module
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
# control and status module
self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Add debug interface if the CPU has one ---------------------------------------------------
if hasattr(self.cpu, "debug_bus"):
self.register_mem(
name="vexriscv_debug",
address=0xf00f0000,
interface=self.cpu.debug_bus,
size=0x100)
# Memory mapped SPI Flash ------------------------------------------------------------------
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
self.register_mem("spiflash", self.mem_map["spiflash"],
self.spiflash.bus, size=platform.spiflash_total_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
self.add_constant("DEVICE_TREE_IMAGE_FLASH_OFFSET",0x00000000)
self.add_constant("EMULATOR_IMAGE_FLASH_OFFSET",0x4000)
self.add_constant("KERNEL_IMAGE_FLASH_OFFSET",0x30000)
self.add_constant("ROOTFS_IMAGE_FLASH_OFFSET",0x5b0000)
# Take Ethernet Phy out of reset for SYSCLK of 125 Mhz
gmii_rst_n = platform.request("gmii_rst_n")
self.comb += [
gmii_rst_n.eq(1)
]
