def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# mac
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus,
0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 25e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 25e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
platform = nexys4ddr.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR2",
nphases=2,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT47H64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_ethernet(phy=self.ethphy)
def __init__(self, phy, clk_freq):
platform = CorePlatform()
SoCCore.__init__(self,
platform,
clk_freq=clk_freq,
cpu_type=None,
integrated_rom_size=0x0,
integrated_sram_size=0x0,
integrated_main_ram_size=0x0,
csr_address_width=14,
csr_data_width=8,
with_uart=False,
with_timer=False)
self.submodules.crg = CRG(platform.request("sys_clock"),
platform.request("sys_reset"))
# ethernet
if phy == "MII":
self.submodules.ethphy = LiteEthPHYMII(
platform.request("mii_eth_clocks"),
platform.request("mii_eth"))
elif phy == "RMII":
self.submodules.ethphy = LiteEthPHYRMII(
platform.request("rmii_eth_clocks"),
platform.request("rmii_eth"))
elif phy == "GMII":
self.submodules.ethphy = LiteEthPHYGMII(
platform.request("gmii_eth_clocks"),
platform.request("gmii_eth"))
elif phy == "RGMII":
self.submodules.ethphy = LiteEthPHYRGMII(
platform.request("rgmii_eth_clocks"),
platform.request("rgmii_eth"))
else:
ValueError("Unsupported " + phy + " PHY")
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
platform = netv2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = K4B2G1646F(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRMII(
self.platform.request("eth_clocks"), self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 12.5e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs):
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
self.submodules.ethphy = LiteEthPHYRMII(
self.platform.request("eth_clocks"), self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 12.5e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, *args, **kwargs):
# Need a larger integrated ROM to fit the BIOS with TFTP support.
dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYRMII(
platform.request("eth_clocks"),
platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 40.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 40.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self,
sys_clk_freq=int(75e6),
with_ethernet=False,
with_etherbone=False,
with_led_chaser=True,
with_video_terminal=False,
with_video_framebuffer=False,
**kwargs):
platform = nexys4ddr.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Nexys4DDR",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR2",
nphases=2,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT47H64M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"),
clock_domain="vga")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
variant="a7-35",
sys_clk_freq=int(100e6),
with_pcie=False,
with_ethernet=False,
**kwargs):
platform = netv2.Platform(variant=variant)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on NeTV2",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=K4B2G1646F(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1, max_pending_requests=2)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_spi_xip=False,
**kwargs):
platform = netv2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=K4B2G1646F(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# SPI XIP ----------------------------------------------------------------------------------
if with_spi_xip:
from litespi import LiteSPI
from litespi.phy.generic import LiteSPIPHY
spi_xip_size = 1024 * 1024 * 8
self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x"))
self.submodules.spictl = LiteSPI(phy=self.spiphy,
endianness=self.cpu.endianness)
spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None),
size=spi_xip_size,
cached=False)
self.bus.add_slave(name="spixip",
slave=self.spictl.bus,
region=spi_xip_region)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self,
sys_clk_freq=int(75e6),
with_led_chaser=True,
with_ethernet=False,
with_etherbone=False,
with_video_terminal=False,
with_video_framebuffer=False,
**kwargs):
platform = digilent_nexys4.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Nexys4",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Cellular RAM -------------------------------------------------------------------------------
addCellularRAM(self, platform, "main_ram", 0x40000000)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"),
clock_domain="vga")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
platform = nexys4ddr.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Nexys4DDR",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR2",
nphases=2,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT47H64M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(16)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, phy, clk_freq):
platform = CorePlatform()
SoCMini.__init__(self, platform, clk_freq=clk_freq)
self.submodules.crg = CRG(platform.request("sys_clock"),
platform.request("sys_reset"))
# ethernet
if phy == "mii":
ethphy = LiteEthPHYMII(platform.request("mii_eth_clocks"),
platform.request("mii_eth"))
elif phy == "rmii":
ethphy = LiteEthPHYRMII(platform.request("rmii_eth_clocks"),
platform.request("rmii_eth"))
elif phy == "gmii":
ethphy = LiteEthPHYGMII(platform.request("gmii_eth_clocks"),
platform.request("gmii_eth"))
elif phy == "rgmii":
ethphy = LiteEthPHYRGMII(platform.request("rgmii_eth_clocks"),
platform.request("rgmii_eth"))
else:
raise ValueError("Unsupported " + phy + " PHY");
self.submodules.ethphy = ethphy
self.add_csr("ethphy")
def __init__(self,
sys_clk_freq=int(75e6),
with_ethernet=False,
with_vga=False,
**kwargs):
platform = nexys4ddr.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Nexys4DDR",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR2",
nphases=2,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT47H64M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# VGA terminal -----------------------------------------------------------------------------
if with_vga:
self.submodules.terminal = terminal = Terminal()
self.bus.add_slave("terminal",
self.terminal.bus,
region=SoCRegion(origin=0x30000000,
size=0x10000))
vga_pads = platform.request("vga")
self.comb += [
vga_pads.vsync.eq(terminal.vsync),
vga_pads.hsync.eq(terminal.hsync),
vga_pads.red.eq(terminal.red[4:8]),
vga_pads.green.eq(terminal.green[4:8]),
vga_pads.blue.eq(terminal.blue[4:8])
]
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
# Timer ---------------------------------------------------------------
# If timer0 is enabled ensure that update timer is available also
if "with_timer" in kwargs:
with_timer = kwargs.get("with_timer")
if with_timer:
kwargs["timer_uptime"] = True
self.platform = Platform
# SoCCore -------------------------------------------------------------
SoCCore.__init__(self, self.platform, clk_freq=sys_clk_freq, **kwargs)
#self.mem_map = {**self.mem_map, **{
# "spiflash": 0xd0_000_000
#}}
# CRG -----------------------------------------------------------------
eth0_clock = self.platform.request("eth_clocks_ext", 0)
eth1_clock = self.platform.request("eth_clocks_ext", 1)
eth2_clock = self.platform.request("eth_clocks_ext", 2)
eth3_clock = self.platform.request("eth_clocks_ext", 3)
self.submodules.crg = _CRG(self.platform, sys_clk_freq, eth0_clock,
eth1_clock, eth2_clock, eth3_clock)
# DDR3 SDRAM ----------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
self.platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# SPI Flash -----------------------------------------------------------
# Disabled due to rom size limitations
#SPIFLASH_PAGE_SIZE = 256
#SPIFLASH_SECTOR_SIZE = 64 * 1024
#SPIFLASH_DUMMY_CYCLES = 11
#self.add_spi_flash(dummy_cycles=SPIFLASH_DUMMY_CYCLES)
#self.add_constant("SPIFLASH_PAGE_SIZE", SPIFLASH_PAGE_SIZE)
#self.add_constant("SPIFLASH_SECTOR_SIZE", SPIFLASH_SECTOR_SIZE)
## Place firmware in second half of 16MB SPI flash. First half is
## used for FPGA bitstream
#self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map["spiflash"] + 0x800000)
# SPI SD-Card ---------------------------------------------------------
self.add_spi_sdcard(name="spisdcard", spi_clk_freq=400e3)
# Hello World ---------------------------------------------------------
self.submodules.hello = Hello()
self.csr.add("hello")
# GPIO ----------------------------------------------------------------
#pd = self.platform.request("pmodd")
#self.submodules.pmodd = GPIOInOut(in_signal=pd, out_signal=pd)
#self.csr.add("pmodd")
# Misc GPIO -----------------------------------------------------------
self.submodules.leds = GPIOOut(
Cat(platform_request_all(self.platform, "user_led")))
self.add_csr("leds")
rgb_led_pads = self.platform.request("rgb_led", 0)
for n in "rgb":
setattr(self.submodules, "rgb_led_{}0".format(n),
PWM(getattr(rgb_led_pads, n)))
self.add_csr("rgb_led_{}0".format(n))
self.submodules.switches = GPIOIn(
Cat(platform_request_all(self.platform, "user_sw")))
self.add_csr("switches")
# Ethernet ------------------------------------------------------------
# Loval IP4 address of Ethernet interface 1 (10.0.0.50)
self.add_constant("LOCALIP1", 10)
self.add_constant("LOCALIP2", 0)
self.add_constant("LOCALIP3", 0)
self.add_constant("LOCALIP4", 50)
# IP4 Address of TFTP boot server (10.0.0.100)
self.add_constant("REMOTEIP1", 10)
self.add_constant("REMOTEIP2", 0)
self.add_constant("REMOTEIP3", 0)
self.add_constant("REMOTEIP4", 100)
# Ethernet interface 0 (used for TFTP boot).
# Name it "ethphy" and "ethmac" to be recognized by
# BIOS for tftp boot option. Also if it is the only
# interface in the system you MUST remove the 'phy_cd'
# attribute from add_ethernet (or set it to "eth") otherwise
# build fails. When using external ref_clock set clock_pads
# to None and provide a clock domain name for the external
# clock via refclk_cd.
self.submodules.ethphy = LiteEthPHYRMII(clock_pads=None,
pads=self.platform.request(
"eth", 0),
with_hw_init_reset=True,
refclk_cd="eth0")
self.add_csr("ethphy")
self.add_ethernet(name="ethmac", phy=self.ethphy, phy_cd="ethphy_eth")
# Ethernet interface 1
self.submodules.ethphy1 = LiteEthPHYRMII(clock_pads=None,
pads=self.platform.request(
"eth", 1),
with_hw_init_reset=True,
refclk_cd="eth1")
self.add_csr("ethphy1")
self.add_ethernet(name="ethmac1",
phy=self.ethphy1,
phy_cd="ethphy1_eth")
# Ethernet interface 2
self.submodules.ethphy2 = LiteEthPHYRMII(clock_pads=None,
pads=self.platform.request(
"eth", 2),
with_hw_init_reset=True,
refclk_cd="eth2")
self.add_csr("ethphy2")
self.add_ethernet(name="ethmac2",
phy=self.ethphy2,
phy_cd="ethphy2_eth")
# Ethernet interface 3
self.submodules.ethphy3 = LiteEthPHYRMII(clock_pads=None,
pads=self.platform.request(
"eth", 3),
with_hw_init_reset=True,
refclk_cd="eth3")
self.add_csr("ethphy3")
# Disabled becaused used for etherbone down below
#self.add_ethernet(name="ethmac3", phy=self.ethphy3, phy_cd="ethphy3_eth")
# ticker --------------------------------------------------------------
self.submodules.ticker = Ticker(CLK_FRQ_HZ=sys_clk_freq)
self.csr.add("ticker")
# random --------------------------------------------------------------
self.submodules.random = Random()
self.csr.add("random")
# lite-scope debugger -------------------------------------------------
self.add_etherbone(phy=self.ethphy3,
phy_cd="ethphy3_eth",
ip_address="10.0.0.42",
mac_address=0x10e2d5000001,
udp_port=4711)
# CPU signals
analyzer_signals = [
self.cpu.ibus.stb, self.cpu.ibus.cyc, self.cpu.ibus.adr,
self.cpu.ibus.we, self.cpu.ibus.ack, self.cpu.ibus.sel,
self.cpu.ibus.dat_w, self.cpu.ibus.dat_r
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self, platform,
with_sdram=True,
with_ethernet=False,
with_etherbone=True,
with_sdcard=True,
with_pcie=False,
with_hdmi_in0=False, with_hdmi_out0=False,
with_hdmi_in1=False, with_hdmi_out1=False,
with_interboard_communication=False):
assert not (with_pcie and with_interboard_communication)
sys_clk_freq = int(100e6)
sd_freq = int(100e6)
SoCSDRAM.__init__(self, platform, sys_clk_freq,
#cpu_type="vexriscv", l2_size=32,
cpu_type=None, l2_size=32,
#csr_data_width=8, csr_address_width=14,
csr_data_width=32, csr_address_width=14,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
integrated_main_ram_size=0x8000 if not with_sdram else 0,
ident="NeTV2 LiteX Test SoC", ident_version=True,
reserve_nmi_interrupt=False)
# crg
self.submodules.crg = CRG(platform, sys_clk_freq)
# dnax
self.submodules.dna = dna.DNA()
# xadc
self.submodules.xadc = xadc.XADC()
# icap
self.submodules.icap = ICAP(platform)
# flash
self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6))
# sdram
if with_sdram:
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6)
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# ethernet
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# etherbone
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq)
self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master"))
self.add_wb_master(self.cpu.wishbone.bus)
#self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
#self.add_wb_master(self.etherbone.wishbone.bus)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# sdcard
self.submodules.sdclk = SDClockerS7()
self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device)
self.submodules.sdcore = SDCore(self.sdphy)
self.submodules.sdtimer = Timer()
self.submodules.bist_generator = BISTBlockGenerator(random=True)
self.submodules.bist_checker = BISTBlockChecker(random=True)
self.comb += [
self.sdcore.source.connect(self.bist_checker.sink),
self.bist_generator.source.connect(self.sdcore.sink)
]
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq)
self.crg.cd_sys.clk.attr.add("keep")
self.sdclk.cd_sd.clk.attr.add("keep")
self.sdclk.cd_sd_fb.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.sdclk.cd_sd.clk,
self.sdclk.cd_sd_fb.clk)
# pcie
if with_pcie:
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2"))
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True)
# pcie wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000)
self.add_wb_master(self.pcie_bridge.wishbone)
# pcie dma
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# interboard communication
if with_interboard_communication:
self.clock_domains.cd_refclk = ClockDomain()
self.submodules.refclk_pll = refclk_pll = S7PLL()
refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6)
refclk_pll.create_clkout(self.cd_refclk, 125e6)
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# qpll
qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9)
print(qpll)
self.submodules += qpll
# gtp
gtp = GTP(qpll,
platform.request("interboard_comm_tx"),
platform.request("interboard_comm_rx"),
sys_clk_freq,
clock_aligner=True, internal_loopback=False)
self.submodules += gtp
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)
# send counter to other-board
self.comb += [
gtp.encoder.k[0].eq(1),
gtp.encoder.d[0].eq((5 << 5) | 28),
gtp.encoder.k[1].eq(0),
gtp.encoder.d[1].eq(counter[26:])
]
# receive counter and display it on leds
self.comb += [
platform.request("user_led", 3).eq(gtp.rx_ready),
platform.request("user_led", 4).eq(gtp.decoders[1].d[0]),
platform.request("user_led", 5).eq(gtp.decoders[1].d[1])
]
gtp.cd_tx.clk.attr.add("keep")
gtp.cd_rx.clk.attr.add("keep")
platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.cd_tx.clk,
gtp.cd_rx.clk)
# hdmi in 0
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk),
for clk in [self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6))
# hdmi out 0
if with_hdmi_out0:
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
platform.request("hdmi_out", 0),
hdmi_out0_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# hdmi in 1
if with_hdmi_in1:
hdmi_in1_pads = platform.request("hdmi_in", 1)
self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in1 = HDMIIn(
hdmi_in1_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk),
for clk in [self.hdmi_in1.clocking.cd_pix.clk,
self.hdmi_in1.clocking.cd_pix1p25x.clk,
self.hdmi_in1.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6))
# hdmi out 1
if with_hdmi_out1:
hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True)
self.submodules.hdmi_out1 = VideoOut(
platform.device,
platform.request("hdmi_out", 1),
hdmi_out1_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# led blinking (sys)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# led blinking (pcie)
if with_pcie:
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# led blinking (sdcard)
if with_sdcard:
sd_counter = Signal(32)
self.sync.sd += sd_counter.eq(sd_counter + 1)
self.comb += platform.request("user_led", 1).eq(sd_counter[26])
def __init__(self,
platform,
with_cpu=True,
with_sdram=True,
with_etherbone=True,
with_gtp=True,
gtp_connector="pcie",
gtp_refclk="pcie",
gtp_linerate=5e9,
with_gtp_bist=True,
with_gtp_freqmeter=True,
with_record=True):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv" if with_cpu else None,
csr_data_width=32,
with_uart=with_cpu,
uart_name="crossover",
integrated_rom_size=0x8000 if with_cpu else 0x0000,
integrated_main_ram_size=0x1000 if not with_sdram else 0x0000,
ident="PCIe Analyzer LiteX SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# ethphy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# ethcore
self.submodules.ethcore = LiteEthUDPIPCore(
phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 50e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 50e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# GTP RefClk -------------------------------------------------------------------------------
if with_gtp:
assert gtp_refclk in ["pcie", "internal"]
if gtp_refclk == "pcie":
refclk = Signal()
refclk_freq = 100e6
refclk_pads = platform.request("pcie_refclk")
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
else:
refclk = Signal()
refclk_freq = 100e6
self.comb += refclk.eq(ClockSignal("clk100"))
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]"
)
# GTP PLL ----------------------------------------------------------------------------------
if with_gtp:
qpll = GTPQuadPLL(refclk, refclk_freq, gtp_linerate)
print(qpll)
self.submodules += qpll
# GTPs -------------------------------------------------------------------------------------
if with_gtp:
for i in range(2):
tx_pads = platform.request(gtp_connector + "_tx", i)
rx_pads = platform.request(gtp_connector + "_rx", i)
gtp = GTP(qpll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True)
gtp.add_stream_endpoints()
setattr(self.submodules, "gtp" + str(i), gtp)
platform.add_period_constraint(gtp.cd_tx.clk,
1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk,
1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk)
# GTPs FreqMeters --------------------------------------------------------------------------
if with_gtp_freqmeter:
self.submodules.gtp0_tx_freq = FreqMeter(ClockSignal("gtp0_tx"))
self.submodules.gtp0_rx_freq = FreqMeter(ClockSignal("gtp0_rx"))
self.submodules.gtp1_tx_freq = FreqMeter(ClockSignal("gtp1_tx"))
self.submodules.gtp1_rx_freq = FreqMeter(ClockSignal("gtp1_rx"))
self.add_csr("gtp0_tx_freq")
self.add_csr("gtp0_rx_freq")
self.add_csr("gtp1_tx_freq")
self.add_csr("gtp1_rx_freq")
# GTPs BIST --------------------------------------------------------------------------------
if with_gtp_bist:
self.submodules.gtp0_tx_bist = GTPTXBIST(self.gtp0, "gtp0_tx")
self.submodules.gtp0_rx_bist = GTPRXBIST(self.gtp0, "gtp0_rx")
self.submodules.gtp1_tx_bist = GTPTXBIST(self.gtp1, "gtp1_tx")
self.submodules.gtp1_rx_bist = GTPRXBIST(self.gtp1, "gtp1_rx")
self.add_csr("gtp0_tx_bist")
self.add_csr("gtp0_rx_bist")
self.add_csr("gtp1_tx_bist")
self.add_csr("gtp1_rx_bist")
# Record -----------------------------------------------------------------------------------
# FIXME: use better data/ctrl packing (or separate recorders)
if with_record:
# Convert RX stream from 16-bit@250MHz to 64-bit@sys_clk
rx_converter = stream.StrideConverter([("data", 16), ("ctrl", 2)],
[("data", 96), ("ctrl", 12)],
reverse=False)
rx_converter = ClockDomainsRenamer("gtp0_rx")(rx_converter)
self.submodules.rx_converter = rx_converter
rx_cdc = stream.AsyncFIFO([("data", 96), ("ctrl", 12)],
8,
buffered=True)
rx_cdc = ClockDomainsRenamer({
"write": "gtp0_rx",
"read": "sys"
})(rx_cdc)
self.submodules.rx_cdc = rx_cdc
# RX DMA Recorder
self.submodules.rx_dma_recorder = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port("write", 128))
self.rx_dma_recorder.add_csr()
self.add_csr("rx_dma_recorder")
self.comb += [
gtp.source.connect(rx_converter.sink),
rx_converter.source.connect(rx_cdc.sink),
self.rx_dma_recorder.sink.valid.eq(rx_cdc.source.valid),
self.rx_dma_recorder.sink.data[0:96].eq(rx_cdc.source.data),
self.rx_dma_recorder.sink.data[96:108].eq(rx_cdc.source.ctrl),
]
def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs):
platform = de0nano.Platform()
platform.toolchain.additional_qsf_commands = [
'set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"',
]
platform.toolchain.additional_sdc_commands = [
'create_clock -name eth_rx_clk -period 20 [get_ports eth_clocks_ref_clk]',
'create_clock -name eth_rx_clk_virt -period 20',
'derive_clock_uncertainty',
'set CLKAs_max 0.0',
'set CLKAs_min 0.0',
'set CLKAd_max 1.13',
'set CLKAd_min 0.87',
'set tCOa_max 16',
'set tCOa_min 1',
'set BDa_max 1.13',
'set BDa_min 0.87',
'set_input_delay -clock eth_rx_clk_virt -max [expr $CLKAs_max + $tCOa_max + $BDa_max - $CLKAd_min] [get_ports {eth_rx_data[*] eth_crs_dv}]',
'set_input_delay -clock eth_rx_clk_virt -min [expr $CLKAs_min + $tCOa_min + $BDa_min - $CLKAd_max] [get_ports {eth_rx_data[*] eth_crs_dv}]',
]
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(
self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE0-Nano",
ident_version=True,
cpu_type="vexriscv_smp",
cpu_variant="linux",
max_sdram_size=0x40000000, # Limit mapped SDRAM to 1GB.
**kwargs)
# Add linker region for OpenSBI
self.add_memory_region("opensbi",
self.mem_map["main_ram"] + 0x00f00000,
0x80000,
type="cached+linker")
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16160(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# UART -------------------------------------------------------------------------------------
_uart_jp_ios = [("uart", 0,
Subsignal("tx", Pins("JP1:34"),
IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("JP1:32"),
IOStandard("3.3-V LVTTL")))]
self.platform.add_extension(_uart_jp_ios)
self.add_uart(name="uart", baudrate=921600, fifo_depth=1024)
# Leds -------------------------------------------------------------------------------------
led_pads = platform.request_all("user_led")
self.submodules.leds = GPIOOut(led_pads)
self.add_constant("LEDS_NGPIO", len(led_pads))
# Keys -------------------------------------------------------------------------------------
switches_pads = self.platform.request_all("key")
self.submodules.switches = GPIOIn(pads=switches_pads, with_irq=True)
self.irq.add("switches", use_loc_if_exists=True)
self.add_constant("SWITCHES_NGPIO", len(switches_pads))
# RMII Ethernet ----------------------------------------------------------------------------
_ethernet_jp_ios = [
(
"eth_clocks",
0,
Subsignal("ref_clk", Pins("JP2:34")),
IOStandard("3.3-V LVTTL"),
),
(
"eth",
0,
#Subsignal("rst_n", Pins("")),
Subsignal("rx_data", Pins("JP2:36 JP2:35")),
Subsignal("crs_dv", Pins("JP2:33")),
Subsignal("tx_en", Pins("JP2:38")),
Subsignal("tx_data", Pins("JP2:37 JP2:40")),
Subsignal("mdc", Pins("JP2:31")),
Subsignal("mdio", Pins("JP2:32")),
#Subsignal("rx_er", Pins("")),
#Subsignal("int_n", Pins("")),
IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_ethernet_jp_ios)
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
refclk_cd=None,
)
self.add_ethernet(phy=self.ethphy, nrxslots=4, ntxslots=2)
# SD Card ----------------------------------------------------------------------------------
_sdcard_jp_ios = [
(
"sdcard",
0,
Subsignal("data", Pins("JP2:14 JP2:24 JP2:22 JP2:20"),
Misc("WEAK_PULL_UP_RESISTOR ON")),
Subsignal("cmd", Pins("JP2:16"),
Misc("WEAK_PULL_UP_RESISTOR ON")),
Subsignal("clk", Pins("JP2:18")),
Subsignal("cd", Pins("JP2:26")),
Misc("FAST_OUTPUT_REGISTER ON"),
IOStandard("3.3-V LVTTL"),
),
]
#_sdcard_jp_ios = [
# ("spisdcard", 0,
# Subsignal("miso", Pins("JP2:14"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Subsignal("mosi", Pins("JP2:16"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Subsignal("clk", Pins("JP2:18")),
# Subsignal("cs_n", Pins("JP2:20"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Misc("FAST_OUTPUT_REGISTER ON"),
# IOStandard("3.3-V LVTTL"),
# ),
#]
self.platform.add_extension(_sdcard_jp_ios)
self.add_sdcard()
#self.add_spi_sdcard()
# EPCS ------------------------------------------------------------------------------------
_spi_flash_ios = [
("spiflash", 0, Subsignal("miso", Pins("H2")),
Subsignal("clk", Pins("H1")), Subsignal("cs_n", Pins("D2")),
Subsignal("mosi", Pins("C1")), IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_spi_flash_ios)
self.add_spi_flash(mode="1x", dummy_cycles=8)
# I2C ADXL345 -----------------------------------------------------------------------------
_i2c_ios = [
("i2c_onboard", 0, Subsignal("scl", Pins("F2")),
Subsignal("sda", Pins("F1")), IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_i2c_ios)
self.submodules.i2c0 = I2CMaster(
self.platform.request("i2c_onboard", 0))
adxl_pads = self.platform.request("acc")
self.comb += adxl_pads.cs_n.eq(1)
# ADC -------------------------------------------------------------------------------------
_spi_ios = [("adc128s", 0, Subsignal("cs_n", Pins("A10")),
Subsignal("mosi",
Pins("B10")), Subsignal("clk", Pins("B14")),
Subsignal("miso", Pins("A9")), IOStandard("3.3-V LVTTL"))]
self.platform.add_extension(_spi_ios)
spi_pads = self.platform.request("adc128s")
self.submodules.spi = SPIMaster(spi_pads, 8, self.clk_freq, 1e6)
self.add_csr("spi")
# interrupts ------------------------------------------------------------------------------
#_interrupts_jp_ios = [
# ("interrupt", 0, Pins("JP2:1"), IOStandard("3.3-V LVTTL")),
# ("interrupt", 1, Pins("JP2:26"), IOStandard("3.3-V LVTTL")),
#]
#self.platform.add_extension(_interrupts_jp_ios)
#interrupts_pads = self.platform.request_all("interrupt")
interrupts_pads = adxl_pads.int
self.submodules.interrupts = GPIOIn(interrupts_pads, with_irq=True)
self.irq.add("interrupts", use_loc_if_exists=True)
self.add_constant("INTERRUPTS_NGPIO", len(interrupts_pads))
def __init__(self,
platform,
with_cpu=True,
with_sdram=True,
with_etherbone=True,
with_pcie=True,
with_sdram_dmas=False,
with_hdmi_in0=True,
with_hdmi_out0=True):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv" if with_cpu else None,
cpu_variant="lite",
l2_size=128,
csr_data_width=32,
with_uart=with_cpu,
uart_name="crossover",
integrated_rom_size=0x8000 if with_cpu else 0x0000,
integrated_main_ram_size=0x1000 if not with_sdram else 0x0000,
ident="NeTV2 LiteX SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DNA --------------------------------------------------------------------------------------
self.submodules.dna = DNA()
self.dna.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
self.add_csr("dna")
# XADC -------------------------------------------------------------------------------------
self.submodules.xadc = XADC()
self.add_csr("xadc")
# ICAP -------------------------------------------------------------------------------------
self.submodules.icap = ICAP(platform)
self.icap.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
self.add_csr("icap")
# Flash ------------------------------------------------------------------------------------
self.submodules.flash = S7SPIFlash(platform.request("flash"),
sys_clk_freq, 25e6)
self.add_csr("flash")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# ethphy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# ethcore
self.submodules.ethcore = LiteEthUDPIPCore(
phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 50e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 50e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
# PHY ----------------------------------------------------------------------------------
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
data_width=64,
bar0_size=0x20000)
platform.add_false_path_constraint(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# Endpoint -----------------------------------------------------------------------------
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# Wishbone bridge ----------------------------------------------------------------------
self.submodules.pcie_bridge = LitePCIeWishboneBridge(
self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0 ---------------------------------------------------------------------------------
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma0")
# DMA1 ---------------------------------------------------------------------------------
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2)
# MSI ----------------------------------------------------------------------------------
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# FIXME : Dummy counter capture, connect to HDMI In ------------------------------------
pcie_dma0_counter = Signal(32)
self.sync += [
self.pcie_dma0.sink.valid.eq(1),
If(self.pcie_dma0.sink.ready,
pcie_dma0_counter.eq(pcie_dma0_counter + 1)),
self.pcie_dma0.sink.data.eq(pcie_dma0_counter)
]
pcie_dma1_counter = Signal(32)
self.sync += [
self.pcie_dma1.sink.valid.eq(1),
If(self.pcie_dma1.sink.ready,
pcie_dma1_counter.eq(pcie_dma1_counter + 2)),
self.pcie_dma1.sink.data.eq(pcie_dma1_counter)
]
# SDRAM DMAs -------------------------------------------------------------------------------
if with_sdram_dmas:
self.submodules.sdram_reader = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.sdram_reader.add_csr()
self.add_csr("sdram_reader")
self.submodules.sdram_writer = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.sdram_writer.add_csr()
self.add_csr("sdram_writer")
# HDMI In 0 --------------------------------------------------------------------------------
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.add_csr("hdmi_in0_freq")
self.submodules.hdmi_in0 = HDMIIn(
pads=hdmi_in0_pads,
dram_port=self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.add_csr("hdmi_in0")
self.add_csr("hdmi_in0_edid_mem")
self.comb += self.hdmi_in0_freq.clk.eq(
self.hdmi_in0.clocking.cd_pix.clk),
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk)
self.platform.add_period_constraint(
platform.lookup_request("hdmi_in", 0).clk_p, 1e9 / 74.25e6)
# HDMI Out 0 -------------------------------------------------------------------------------
if with_hdmi_out0:
self.submodules.hdmi_out0 = VideoOut(
device=platform.device,
pads=platform.request("hdmi_out", 0),
dram_port=self.sdram.crossbar.get_port(
mode="read",
data_width=16,
clock_domain="hdmi_out0_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=512)
self.add_csr("hdmi_out0")
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# # #
pix_freq = 148.50e6
########## hdmi in 0 (raw tmds)
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FrequencyMeter(period=self.clk_freq)
self.submodules.hdmi_in0 = hdmi_in0 = HDMIIn(hdmi_in0_pads,
device="xc7",
split_mmcm=True,
hdmi=True)
self.comb += self.hdmi_in0_freq.clk.eq(
self.hdmi_in0.clocking.cd_pix.clk)
# don't add clock timings here, we add a root clock constraint that derives the rest automatically
# define path constraints individually to sysclk to avoid accidentally declaring other inter-clock paths as false paths
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix5x.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix_o.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix5x_o.clk)
hdmi_out0_pads = platform.request("hdmi_out", 0)
self.submodules.hdmi_out0_clk_gen = S7HDMIOutEncoderSerializer(
hdmi_out0_pads.clk_p, hdmi_out0_pads.clk_n, bypass_encoder=True)
self.comb += self.hdmi_out0_clk_gen.data.eq(
Signal(10, reset=0b0000011111))
self.submodules.hdmi_out0_phy = S7HDMIOutPHY(hdmi_out0_pads,
mode="raw")
# hdmi over
self.comb += [
platform.request("hdmi_sda_over_up").eq(0),
platform.request("hdmi_sda_over_dn").eq(0),
]
platform.add_platform_command(
"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets hdmi_in_ibufds/ob]"
)
# extract timing info from HDMI input 0, and put it into a stream that we can pass later on as a genlock object
self.hdmi_in0_timing = hdmi_in0_timing = stream.Endpoint(
frame_timing_layout)
self.sync.pix_o += [
hdmi_in0_timing.de.eq(self.hdmi_in0.syncpol.de),
hdmi_in0_timing.hsync.eq(self.hdmi_in0.syncpol.hsync),
hdmi_in0_timing.vsync.eq(self.hdmi_in0.syncpol.vsync),
If(
self.hdmi_in0.syncpol.valid_o,
hdmi_in0_timing.valid.eq(1),
).Else(hdmi_in0_timing.valid.eq(0), )
]
early_line_end = Signal()
self.comb += early_line_end.eq(hdmi_in0_timing.de
& ~self.hdmi_in0.syncpol.de)
########## hdmi in 1
hdmi_in1_pads = platform.request("hdmi_in", 1)
self.submodules.hdmi_in1_freq = FrequencyMeter(period=self.clk_freq)
self.submodules.hdmi_in1 = HDMIIn(
hdmi_in1_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=1024,
device="xc7",
split_mmcm=False,
mode="rgb",
hdmi=True)
self.comb += self.hdmi_in1_freq.clk.eq(
self.hdmi_in1.clocking.cd_pix.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in1.clocking.cd_pix.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in1.clocking.cd_pix1p25x.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in1.clocking.cd_pix5x.clk)
######## Constraints
# instantiate fundamental clocks -- Vivado will derive the rest via PLL programmings
self.platform.add_platform_command(
"create_clock -name clk50 -period 20.0 [get_nets clk50]")
self.platform.add_platform_command(
"create_clock -name hdmi_in0_clk_p -period 6.734006734006734 [get_nets hdmi_in0_clk_p]"
)
self.platform.add_platform_command(
"create_clock -name hdmi_in1_clk_p -period 6.734006734006734 [get_nets hdmi_in1_clk_p]"
)
# exclude all generated clocks from the fundamental HDMI cloks and sys clocks
self.platform.add_platform_command(
"set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_in0_clk_p]] -asynchronous"
)
self.platform.add_platform_command(
"set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_in1_clk_p]] -asynchronous"
)
# make sure derived clocks get named correctly; I think this is now being done right without these args
# self.platform.add_platform_command("create_generated_clock -name hdmi_in0_pix_clk [get_pins MMCME2_ADV/CLKOUT0]")
# self.platform.add_platform_command("create_generated_clock -name hdmi_in0_pix1p25x_clk [get_pins MMCME2_ADV/CLKOUT1]")
# self.platform.add_platform_command("create_generated_clock -name hdmi_in0_pix5x_clk [get_pins MMCME2_ADV/CLKOUT2]")
# self.platform.add_platform_command("create_generated_clock -name pix_o_clk [get_pins PLLE2_ADV/CLKOUT0]")
# self.platform.add_platform_command("create_generated_clock -name pix5x_o_clk [get_pins PLLE2_ADV/CLKOUT2]")
#
# self.platform.add_platform_command("create_generated_clock -name hdmi_in1_pix_clk [get_pins MMCME2_ADV_1/CLKOUT0]")
# self.platform.add_platform_command("create_generated_clock -name hdmi_in1_pix1p25x_clk [get_pins MMCME2_ADV_1/CLKOUT1]")
# self.platform.add_platform_command("create_generated_clock -name hdmi_in1_pix5x_clk [get_pins MMCME2_ADV_1/CLKOUT2]")
# don't time the high-fanout reset paths
self.platform.add_platform_command(
"set_false_path -through [get_nets hdmi_in1_pix_rst]")
self.platform.add_platform_command(
"set_false_path -through [get_nets hdmi_in0_pix_rst]")
self.platform.add_platform_command(
"set_false_path -through [get_nets hdmi_in1_pix1p25x_rst]")
self.platform.add_platform_command(
"set_false_path -through [get_nets hdmi_in0_pix1p25x_rst]")
self.platform.add_platform_command(
"set_false_path -through [get_nets pix_o_rst]")
self.platform.add_platform_command(
"set_false_path -through [get_nets soc_videooverlaysoc_hdmi_out0_clk_gen_ce]"
) # derived from reset
# gearbox timing is a multi-cycle path: FAST to SLOW synchronous clock domains
self.platform.add_platform_command(
"set_multicycle_path 2 -setup -start -from [get_clocks soc_videooverlaysoc_hdmi_in0_mmcm_clk1] -to [get_clocks soc_videooverlaysoc_hdmi_in0_mmcm_clk0]"
)
self.platform.add_platform_command(
"set_multicycle_path 1 -hold -from [get_clocks soc_videooverlaysoc_hdmi_in0_mmcm_clk1] -to [get_clocks soc_videooverlaysoc_hdmi_in0_mmcm_clk0]"
)
self.platform.add_platform_command(
"set_multicycle_path 2 -setup -start -from [get_clocks soc_videooverlaysoc_hdmi_in1_mmcm_clk1] -to [get_clocks soc_videooverlaysoc_hdmi_in1_mmcm_clk0]"
)
self.platform.add_platform_command(
"set_multicycle_path 1 -hold -from [get_clocks soc_videooverlaysoc_hdmi_in1_mmcm_clk1] -to [get_clocks soc_videooverlaysoc_hdmi_in1_mmcm_clk0]"
)
############### hdmi out 1 (overlay rgb)
out_dram_port = self.sdram.crossbar.get_port(mode="read",
cd="pix_o",
dw=32,
reverse=True)
self.submodules.hdmi_core_out0 = VideoOutCore(
out_dram_port,
mode="rgb",
fifo_depth=1024,
genlock_stream=hdmi_in0_timing)
core_source_valid_d = Signal()
core_source_data_d = Signal(32)
sync_cd = getattr(self.sync, out_dram_port.cd)
sync_cd += [
core_source_valid_d.eq(self.hdmi_core_out0.source.valid),
core_source_data_d.eq(self.hdmi_core_out0.source.data),
]
####### timing stream extraction
timing_rgb_delay = TimingDelayRGB(
4
) # create the delay element with specified delay...note if you say TimingDelay() the code runs happily with no error, because Python doesn't typecheck
timing_rgb_delay = ClockDomainsRenamer("pix_o")(
timing_rgb_delay) # assign a clock domain to the delay element
self.submodules += timing_rgb_delay # DONT FORGET THIS LINE OR ELSE NOTHING HAPPENS....
self.hdmi_out0_rgb = hdmi_out0_rgb = stream.Endpoint(
rgb_layout) # instantiate the input record
self.hdmi_out0_rgb_d = hdmi_out0_rgb_d = stream.Endpoint(
rgb_layout) # instantiate the output record
self.comb += [
self.hdmi_core_out0.source.ready.eq(
1
), # don't forget to tell the upstream component that we're ready, or we get a monochrome screen...
hdmi_out0_rgb.b.eq(
core_source_data_d[0:8]
), # wire up the specific elements of the input record
hdmi_out0_rgb.g.eq(core_source_data_d[8:16]),
hdmi_out0_rgb.r.eq(core_source_data_d[16:24]),
hdmi_out0_rgb.valid.eq(
core_source_valid_d
), # not used, but hook it up anyways in case we need it later...
timing_rgb_delay.sink.eq(
hdmi_out0_rgb), # assign input stream to the delay element
hdmi_out0_rgb_d.eq(timing_rgb_delay.source
) # grab output stream from the delay element
# the output records are directly consumed down below
]
##### HDCP engine
platform.add_source(os.path.join("overlay", "i2c_snoop.v"))
platform.add_source(os.path.join("overlay", "diff_network.v"))
platform.add_source(os.path.join("overlay", "hdcp_block.v"))
platform.add_source(os.path.join("overlay", "hdcp_cipher.v"))
platform.add_source(os.path.join("overlay", "hdcp_lfsr.v"))
platform.add_source(os.path.join("overlay", "shuffle_network.v"))
platform.add_source(os.path.join("overlay", "hdcp_mod.v"))
self.submodules.i2c_snoop = i2c_snoop = I2Csnoop(hdmi_in0_pads)
self.submodules.hdcp = hdcp = HDCP(hdmi_in0_timing)
self.comb += hdcp.line_end.eq(
early_line_end
) # wire up an early line-end signal to meet rekey timing
Aksv14 = Signal()
Aksv14_r = Signal()
self.specials += MultiReg(i2c_snoop.Aksv14_write,
Aksv14,
odomain="pix_o")
self.sync.pix_o += [
Aksv14_r.eq(Aksv14),
hdcp.Aksv14_write.eq(
Aksv14 & ~Aksv14_r), # should be a rising-edge strobe only
# hdcp.hpd.eq(hdmi_in0.edid._hpd_notif.status),
hdcp.hdcp_ena.eq(hdmi_in0.decode_terc4.encrypting_video
| hdmi_in0.decode_terc4.encrypting_data),
hdcp.hpd.eq(hdmi_in0_pads.hpd_notif),
hdcp.An.eq(i2c_snoop.An),
hdcp.ctl_code.eq(hdmi_in0.decode_terc4.ctl_code),
]
self.comb += platform.request("hpd_en").eq(hdcp.hpd_ena.storage)
###### overlay pixel encoders
self.submodules.encoder_red = encoder_red = ClockDomainsRenamer(
"pix_o")(Encoder())
self.submodules.encoder_grn = encoder_grn = ClockDomainsRenamer(
"pix_o")(Encoder())
self.submodules.encoder_blu = encoder_blu = ClockDomainsRenamer(
"pix_o")(Encoder())
self.comb += [
If(
hdcp.Km_valid.
storage, # this is a proxy for HDCP being initialized
encoder_red.d.eq(hdmi_out0_rgb.r
^ hdcp.cipher_stream[16:]), # 23:16
encoder_grn.d.eq(hdmi_out0_rgb.g
^ hdcp.cipher_stream[8:16]), # 15:8
encoder_blu.d.eq(
(hdmi_out0_rgb.b ^ hdcp.cipher_stream[0:8])), # 7:0
# encoder_red.d.eq(hdcp.cipher_stream[16:]), # 23:16
# encoder_grn.d.eq(hdcp.cipher_stream[8:16]), # 15:8
# encoder_blu.d.eq(hdcp.cipher_stream[0:8]), # 7:0
).Else(
encoder_red.d.eq(hdmi_out0_rgb.r),
encoder_grn.d.eq(hdmi_out0_rgb.g),
encoder_blu.d.eq(hdmi_out0_rgb.b),
),
encoder_red.de.eq(1),
encoder_red.c.eq(
0
), # we promise to use this only during video areas, so "c" is always 0
encoder_grn.de.eq(1),
encoder_grn.c.eq(0),
encoder_blu.de.eq(1),
encoder_blu.c.eq(0),
]
# hdmi in to hdmi out
c0_pix_o = Signal(10)
c1_pix_o = Signal(10)
c2_pix_o = Signal(10)
c0 = Signal(10)
c1 = Signal(10)
c2 = Signal(10)
self.comb += [
c0.eq(self.hdmi_in0.syncpol.c0),
c1.eq(self.hdmi_in0.syncpol.c1),
c2.eq(self.hdmi_in0.syncpol.c2),
]
for i in range(
6
): # either 5 or 6; 5 if the first pixel is encrypted by the idle cipher; 6 if the cipher has to be pumped before encryption
c0_next = Signal(10)
c1_next = Signal(10)
c2_next = Signal(10)
self.sync.pix_o += [ # extra delay to absorb cross-domain jitter & routing
c0_next.eq(c0),
c1_next.eq(c1),
c2_next.eq(c2),
]
c0 = c0_next
c1 = c1_next
c2 = c2_next
self.sync.pix_o += [ # extra delay to absorb cross-domain jitter & routing
c0_pix_o.eq(c0_next),
c1_pix_o.eq(c1_next),
c2_pix_o.eq(c2_next)
]
rect_on = Signal()
rect_thresh = Signal(8)
self.submodules.rectangle = rectangle = ClockDomainsRenamer("pix_o")(
RectOpening(hdmi_in0_timing))
self.comb += rect_on.eq(rectangle.rect_on)
self.comb += rect_thresh.eq(rectangle.rect_thresh.storage)
self.sync.pix_o += [
# If(rect_on & (hdmi_out0_rgb_d.r >= 128) & (hdmi_out0_rgb_d.g >= 128) & (hdmi_out0_rgb_d.b >= 128),
If(
rect_on & (hdmi_out0_rgb_d.r >= rect_thresh) &
(hdmi_out0_rgb_d.g >= rect_thresh) &
(hdmi_out0_rgb_d.b >= rect_thresh),
# If(rect_on,
self.hdmi_out0_phy.sink.c0.eq(encoder_blu.out),
self.hdmi_out0_phy.sink.c1.eq(encoder_grn.out),
self.hdmi_out0_phy.sink.c2.eq(encoder_red.out),
).Else(
self.hdmi_out0_phy.sink.c0.eq(c0_pix_o),
self.hdmi_out0_phy.sink.c1.eq(c1_pix_o),
self.hdmi_out0_phy.sink.c2.eq(c2_pix_o),
)
]
self.comb += platform.request("fpga_led2", 0).eq(
self.hdmi_in0.clocking.locked) # RX0 green
self.comb += platform.request("fpga_led3", 0).eq(0) # RX0 red
# self.comb += platform.request("fpga_led4", 0).eq(0) # OV0 red
self.comb += platform.request("fpga_led5", 0).eq(
self.hdmi_in1.clocking.locked) # OV0 green
# analyzer ethernet
from liteeth.phy.rmii import LiteEthPHYRMII
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
fast_eth = False # fast_eth puts etherbone in 100MHz domain; otherwise try to put it in 50MHz domain.
# 100 MHz domain works but timing closure is hard
# 50 MHz domain should also work but I'm not 100% of the syntax to create the clock domains correctly
if fast_eth:
self.submodules.phy = phy = LiteEthPHYRMII(
platform.request("rmii_eth_clocks"),
platform.request("rmii_eth"))
mac_address = 0x1337320dbabe
ip_address = "10.0.11.2"
self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address,
convert_ip(ip_address),
int(100e6))
self.submodules.etherbone = LiteEthEtherbone(self.core.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
else:
phy = LiteEthPHYRMII(platform.request("rmii_eth_clocks"),
platform.request("rmii_eth"))
phy = ClockDomainsRenamer("eth")(phy)
mac_address = 0x1337320dbabe
ip_address = "10.0.11.2"
core = LiteEthUDPIPCore(phy,
mac_address,
convert_ip(ip_address),
int(50e6),
with_icmp=True)
core = ClockDomainsRenamer("eth")(core)
self.submodules += phy, core
etherbone_cd = ClockDomain("etherbone")
self.clock_domains += etherbone_cd
self.comb += [
etherbone_cd.clk.eq(ClockSignal("sys")),
etherbone_cd.rst.eq(ResetSignal("sys"))
]
self.submodules.etherbone = LiteEthEtherbone(core.udp,
1234,
mode="master",
cd="etherbone")
self.add_wb_master(self.etherbone.wishbone.bus)
# Attach the VexRiscv debug bus to RAM
self.register_mem("vexriscv_debug", self.mem_map["vexriscv_debug"],
self.cpu_or_bridge.debug_bus, 0x10)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
self.sync += platform.request("fpga_led4", 0).eq(0) # OV0 red
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
self.platform = Platform
# SoCCore -------------------------------------------------------------
SoCCore.__init__(self, self.platform, clk_freq=sys_clk_freq, **kwargs)
# CRG -----------------------------------------------------------------
self.submodules.crg = _CRG(self.platform, sys_clk_freq)
self.mem_map = {**self.mem_map, **{
"spiflash": 0xd0000000
}}
# DDR3 SDRAM ----------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(self.platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
interface_type = "MEMORY")
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# SPI Flash -----------------------------------------------------------
SPIFLASH_PAGE_SIZE = 256
SPIFLASH_SECTOR_SIZE = 64 * 1024
SPIFLASH_DUMMY_CYCLES = 11
self.add_spi_flash(dummy_cycles=SPIFLASH_DUMMY_CYCLES)
self.add_constant("SPIFLASH_PAGE_SIZE", SPIFLASH_PAGE_SIZE)
self.add_constant("SPIFLASH_SECTOR_SIZE", SPIFLASH_SECTOR_SIZE)
self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map["spiflash"])
# Place firmware in second half of 16MB flash. first half is used
# for FPGA bitstream. For this to work a patched LiteX BIOS version
# is needed. See: https://github.com/rprinz08/litex
self.add_constant("FLASH_BOOT_OFFSET", 0x800000)
# SPI SD-Card ---------------------------------------------------------
self.add_spi_sdcard(name="spisdcard", clk_freq=400e3)
# Hello World ---------------------------------------------------------
self.submodules.hello = Hello()
self.csr.add("hello")
# GPIO ----------------------------------------------------------------
#pd = self.platform.request("pmodd")
#self.submodules.pmodd = GPIOInOut(in_signal=pd, out_signal=pd)
#self.csr.add("pmodd")
# Seven Segment Display -----------------------------------------------
pc = self.platform.request("pmodc")
self.submodules.disp7 = Disp7_stub(pc,
CLK_FRQ_HZ=sys_clk_freq,
REFRESH_CLK_HZ=250, NUM_DIGITS=2,
BCD_MODE=False, FLIP=True)
self.csr.add("disp7")
# Ethernet ------------------------------------------------------------
# Loval IP4 address of Ethernet interface 1 (10.0.0.50)
self.add_constant("LOCALIP1", 10)
self.add_constant("LOCALIP2", 0)
self.add_constant("LOCALIP3", 0)
self.add_constant("LOCALIP4", 50)
# IP4 Address of TFTP boot server (10.0.0.100)
self.add_constant("REMOTEIP1", 10)
self.add_constant("REMOTEIP2", 0)
self.add_constant("REMOTEIP3", 0)
self.add_constant("REMOTEIP4", 100)
# Ethernet interface 0
# Naming this 'ethphy' and 'ethmac' enables BIOS TFTP boot
# functionality. This is disabled here by naming it 'ethphy0' and
# 'ethmac0' as BIOS size wont fit into bitstream ROM. If you want
# this functionality disable other functions like booting from
# SD card
self.submodules.ethphy0 = LiteEthPHYRMII(
clock_pads = self.platform.request("eth0_clocks"),
pads = self.platform.request("eth0"),
name="ethphy0",
with_hw_init_reset=True, cd_name="eth0")
self.add_csr("ethphy0")
self.add_ethernet(name="ethmac0", phy=self.ethphy0)
# Ethernet interface 1
self.submodules.ethphy1 = LiteEthPHYRMII(
clock_pads = self.platform.request("eth1_clocks"),
pads = self.platform.request("eth1"),
name="ethphy1",
with_hw_init_reset=True, cd_name="eth1")
self.add_csr("ethphy1")
self.add_ethernet(name="ethmac1", phy=self.ethphy1)
