def __init__(self, eth_phy=0, **kwargs):
BaseSoC.__init__(self, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy))
self.add_csr("ethphy")
# mac
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self,
platform,
eth_phy=0,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
sys_clk_freq = int(133e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, sys_clk_freq)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = crg = _CRG(platform, sys_clk_freq)
# 1 Gbps Ethernet --------------------------------------------------------------------------
# phy
ethphy = LiteEthPHYRGMII(clock_pads=platform.request(
"eth_clocks", eth_phy),
pads=platform.request("eth", eth_phy))
# core
ethcore = LiteEthUDPIPCore(phy=ethphy,
mac_address=mac_address,
ip_address=ip_address,
clk_freq=sys_clk_freq)
self.submodules += ethphy, ethcore
# timing constraints
platform.add_period_constraint(ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6)
platform.add_false_path_constraints(crg.cd_sys.clk,
ethphy.crg.cd_eth_rx.clk)
# Led --------------------------------------------------------------------------------------
counter = Signal(32)
self.sync += counter.eq(counter + 1)
self.comb += platform.request("user_led").eq(counter[26])
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_led_chaser=True, **kwargs):
platform = linsn_rv901t.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Linsn RV901T",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = M12L64322A(sys_clk_freq, "1:1"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy))
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(
platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] + self.shadow_base,
0x2000)
self.specials += [
Keep(self.ethphy.crg.cd_eth_rx.clk),
Keep(self.ethphy.crg.cd_eth_tx.clk)
]
platform.add_platform_command(
"""
NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE;
NET "{eth_rx_clk}" TNM_NET = "GRPeth_rx_clk";
NET "{eth_tx_clk}" TNM_NET = "GRPeth_tx_clk";
TIMESPEC "TSise_sucks1" = FROM "GRPeth_tx_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPeth_tx_clk" TIG;
TIMESPEC "TSise_sucks3" = FROM "GRPeth_rx_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks4" = FROM "GRPsys_clk" TO "GRPeth_rx_clk" TIG;
PIN "BUFG_4.O" CLOCK_DEDICATED_ROUTE = FALSE;
""",
eth_clocks_rx=platform.lookup_request("eth_clocks").rx,
eth_rx_clk=self.ethphy.crg.cd_eth_rx.clk,
eth_tx_clk=self.ethphy.crg.cd_eth_tx.clk)
def __init__(self,
platform,
eth_phy=0,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
sys_clk_freq = int(133e6)
SoCCore.__init__(self,
platform,
sys_clk_freq,
cpu_type=None,
with_uart=False)
# crg
self.submodules.crg = crg = _CRG(platform, sys_clk_freq)
# 1gbps ethernet
ethphy = LiteEthPHYRGMII(platform.request("eth_clocks", eth_phy),
platform.request("eth", eth_phy))
ethcore = LiteEthUDPIPCore(ethphy, mac_address, convert_ip(ip_address),
sys_clk_freq)
self.submodules += ethphy, ethcore
ethphy.crg.cd_eth_rx.clk.attr.add("keep")
platform.add_period_constraint(ethphy.crg.cd_eth_rx.clk,
period_ns(125e6))
platform.add_false_path_constraints(crg.cd_sys.clk,
ethphy.crg.cd_eth_rx.clk)
# led blink
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led").eq(led_counter[26])
def __init__(self,
sys_clk_freq=int(75e6),
with_ethernet=False,
with_etherbone=False,
eth_phy=0,
with_led_chaser=True,
**kwargs):
platform = linsn_rv901t.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Linsn RV901T",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L64322A(sys_clk_freq, "1:1"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy),
tx_delay=0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy,
with_timing_constraints=False)
if with_etherbone:
self.add_etherbone(phy=self.ethphy,
with_timing_constraints=False)
# Timing Constraints.
platform.add_period_constraint(
platform.lookup_request("eth_clocks", eth_phy).rx, 1e9 / 125e6)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
platform.lookup_request("eth_clocks", eth_phy).rx)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, platform):
sys_clk_freq = int(75e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
cpu_type="picorv32",
integrated_rom_size=0x6000,
integrated_sram_size=8192)
self.submodules.crg = crg = _CRG(platform, sys_clk_freq)
self.submodules.bridge = UARTWishboneBridge(platform.request("dbgserial"), sys_clk_freq, baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
self.submodules.heartbeat = Heartbeat(sys_clk_freq, 0.5, platform.request("user_led"))
self.submodules.j600io = J600IO(
platform.request("U600"),
platform.request("U601"),
platform.request("U604"),
platform.request("U605"),
None)
self.add_wb_slave(mem_decoder(self.mem_map["j600io"]), self.j600io.bus)
self.add_memory_region("j600io", self.mem_map["j600io"] | self.shadow_base, 0x10)
self.submodules.ethphy = LiteEthPHYRGMII(platform.request("eth_clocks", 1), platform.request("eth", 1))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(75e6))
platform.add_false_path_constraints(crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = M12L64322A(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_refresh=False))
