def __init__(self, pads):
        # Control
        self.idle = idle = Signal()
        self.comma = comma = Signal()

        # Datapath
        self.sink = sink = stream.Endpoint([("data", 32)])

        # # #

        # Datapath
        self.submodules.datapath = datapath = TXDatapath(1)
        self.comb += [
            sink.connect(datapath.sink),
            datapath.source.ready.eq(1),
            datapath.idle.eq(idle),
            datapath.comma.eq(comma)
        ]

        # Output data (on rising edge of sys_clk)
        data = Signal()
        self.sync += data.eq(datapath.source.data)
        if hasattr(pads, "tx_p"):
            self.specials += DifferentialOutput(data, pads.tx_p, pads.tx_n)
        else:
            self.comb += pads.tx.eq(data)
Exemplo n.º 2
0
    def __init__(self, pads):
        # Control
        self.idle = idle = Signal()
        self.comma = comma = Signal()

        # Datapath
        self.sink = sink = stream.Endpoint([("data", 32)])

        # # #

        # Datapath
        self.submodules.datapath = datapath = TXDatapath(8)
        self.comb += [
            sink.connect(datapath.sink),
            datapath.source.ready.eq(1),
            datapath.idle.eq(idle),
            datapath.comma.eq(comma)
        ]

        # Output  Data(DDR with sys4x)
        data = Signal()
        self.specials += [
            Instance("OSERDESE3",
                     p_DATA_WIDTH=8,
                     p_INIT=0,
                     p_IS_CLK_INVERTED=0,
                     p_IS_CLKDIV_INVERTED=0,
                     p_IS_RST_INVERTED=0,
                     o_OQ=data,
                     i_RST=ResetSignal("sys"),
                     i_CLK=ClockSignal("sys4x"),
                     i_CLKDIV=ClockSignal("sys"),
                     i_D=datapath.source.data),
            DifferentialOutput(data, pads.tx_p, pads.tx_n)
        ]
Exemplo n.º 3
0
    def __init__(self, pads):
        # Control
        self.idle = idle = Signal()
        self.comma = comma = Signal()

        # Datapath
        self.sink = sink = stream.Endpoint([("data", 32)])

        # # #

        # Datapath
        self.submodules.datapath = datapath = TXDatapath(8)
        self.comb += [
            sink.connect(datapath.sink),
            datapath.source.ready.eq(1),
            datapath.idle.eq(idle),
            datapath.comma.eq(comma)
        ]

        # Data output (DDR with sys4x)
        self.data = data = Signal(8)
        data_serialized = Signal()
        self.comb += data.eq(datapath.source.data)
        self.specials += [
            Instance(
                "OSERDESE2",
                p_DATA_WIDTH=8,
                p_TRISTATE_WIDTH=1,
                p_DATA_RATE_OQ="DDR",
                p_DATA_RATE_TQ="BUF",
                p_SERDES_MODE="MASTER",
                i_OCE=1,
                i_RST=ResetSignal("sys"),
                i_CLK=ClockSignal("sys4x"),
                i_CLKDIV=ClockSignal("sys"),
                i_D1=data[0],
                i_D2=data[1],
                i_D3=data[2],
                i_D4=data[3],
                i_D5=data[4],
                i_D6=data[5],
                i_D7=data[6],
                i_D8=data[7],
                o_OQ=data_serialized,
            ),
            DifferentialOutput(data_serialized, pads.tx_p, pads.tx_n)
        ]