def __init__(self,
sys_clk_freq=int(125e6),
integrated_rom_size=0x8000,
**kwargs):
platform = kcu105.Platform()
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
memtype="DDR4",
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)
sdram_module = EDY4016A(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
main_ram_size_limit=0x40000000)
def main():
parser = argparse.ArgumentParser(description="LitePCIe SoC on KCU105")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--driver",
action="store_true",
help="Generate LitePCIe driver")
parser.add_argument("--load",
action="store_true",
help="Load bitstream (to SRAM)")
parser.add_argument("--speed",
default="gen2",
help="PCIe speed: gen2 (default) or gen3")
parser.add_argument("--nlanes",
default=4,
help="PCIe lanes: 4 (default) or 8")
args = parser.parse_args()
platform = kcu105.Platform()
soc = LitePCIeSoC(platform, speed=args.speed, nlanes=int(args.nlanes))
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(
description="LiteICLink transceiver example on KCU105")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load",
action="store_true",
help="Load bitstream (to SRAM)")
parser.add_argument("--connector",
default="pcie",
help="Connector: pcie (default), sfp0, sfp1 or sma")
parser.add_argument("--linerate",
default="2.5e9",
help="Linerate (default: 2.5e9)")
args = parser.parse_args()
platform = kcu105.Platform()
platform.add_extension(_transceiver_io)
soc = GTHTestSoC(platform,
connector=args.connector,
linerate=float(args.linerate))
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
if "load" in sys.argv[1:]:
load()
platform = kcu105.Platform()
platform.add_extension(_transceiver_io)
soc = GTHTestSoC(platform)
builder = Builder(soc, output_dir="build")
builder.build(build_name="kcu105")
def __init__(self,
sys_clk_freq=int(125e6),
with_ethernet=False,
with_etherbone=False,
**kwargs):
platform = kcu105.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KCU105",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USDDRPHY(
platform.request("ddram"),
memtype="DDR4",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6,
cmd_latency=1)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=EDY4016A(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = KU_1000BASEX(
self.crg.cd_eth.clk,
data_pads=self.platform.request("sfp", 0),
sys_clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def main():
if "load" in sys.argv[1:]:
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
prog.load_bitstream("build/gateware/kcu105.bit")
else:
platform = kcu105.Platform()
soc = GTHTestSoC(platform)
builder = Builder(soc, output_dir="build", compile_gateware=True)
vns = builder.build(build_name="kcu105")
def main():
platform = kcu105.Platform()
if len(sys.argv) < 2:
print("missing target (base or drtio)")
exit()
if sys.argv[1] == "base":
soc = BaseSoC(platform)
elif sys.argv[1] == "drtio":
soc = DRTIOTestSoC(platform)
builder = Builder(soc, output_dir="build_kcu105", csr_csv="test/kcu105/csr.csv")
vns = builder.build()
def __init__(self, uart="crossover", sys_clk_freq=int(125e6)):
platform = kcu105.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
integrated_rom_size=0x8000,
integrated_rom_mode="rw",
csr_data_width=32,
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR4 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
memtype="DDR4",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=EDY4016A(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=0x40000000,
)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
data_pads=self.platform.request(
"sfp", 0),
sys_clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def main():
platform = kcu105.Platform()
platform.add_extension(serdes_io)
if len(sys.argv) < 2:
print("missing target (base or gth or multigth or serdes)")
exit()
if sys.argv[1] == "base":
soc = BaseSoC(platform)
elif sys.argv[1] == "gth":
soc = GTHTestSoC(platform)
elif sys.argv[1] == "multigth":
soc = MultiGTHTestSoC(platform)
elif sys.argv[1] == "serdes":
soc = SERDESTestSoC(platform)
builder = Builder(soc, output_dir="build_kcu105", csr_csv="test/csr.csv")
builder.build()
def main():
parser = argparse.ArgumentParser()
parser.add_argument("--build", action="store_true", help="build bitstream")
parser.add_argument("--load",
action="store_true",
help="load bitstream (to SRAM)")
args = parser.parse_args()
platform = kcu105.Platform()
soc = LitePCIeSoC(platform)
builder = Builder(soc, output_dir="build")
builder.build(build_name="kcu105", run=args.build)
soc.generate_software_headers()
if args.load:
load()
def main():
parser = argparse.ArgumentParser()
parser.add_argument("--build", action="store_true", help="build bitstream")
parser.add_argument("--load",
action="store_true",
help="load bitstream (to SRAM)")
parser.add_argument("--nlanes",
default=1,
help="Number of Gen2 PCIe lanes (1, 4 or 8)")
args = parser.parse_args()
platform = kcu105.Platform()
soc = LitePCIeSoC(platform, nlanes=int(args.nlanes))
builder = Builder(soc, output_dir="build", csr_csv="csr.csv")
builder.build(build_name="kcu105", run=args.build)
soc.generate_software_headers()
if args.load:
load()
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = kcu105.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)
sdram_module = EDY4016A(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)
def __init__(self,
uart="crossover",
sys_clk_freq=int(125e6),
with_bist=False,
with_analyzer=False):
platform = kcu105.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteDRAM bench on KCU105",
ident_version=True,
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
csr_data_width=32,
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR4 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
memtype="DDR4",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=EDY4016A(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=0x40000000,
with_bist=with_bist,
)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
data_pads=self.platform.request(
"sfp", 0),
sys_clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=256,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def main():
soc = ClkGenSoC(kcu105.Platform())
builder = Builder(soc, output_dir="build_clkgen")
builder.build()
