def main():
parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
parser.add_argument(
"--gateware-toolchain",
dest="toolchain",
default="trellis",
help="gateware toolchain to use, trellis (default) or diamond")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq",
default=48e6,
help="system clock frequency (default=48MHz)")
parser.add_argument("--revision",
default="0.2",
help="Board Revision {0.1, 0.2} (default=0.2)")
parser.add_argument("--device",
default="25F",
help="ECP5 device (default=25F)")
parser.add_argument("--sdram-device",
default="MT41K64M16",
help="ECP5 device (default=MT41K64M16)")
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--device", default="85F", help="ECP5 device (default: 85F)")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
device = args.device,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
**soc_core_argdict(args)
)
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument(
"--toolchain",
default="trellis",
help="Gateware toolchain to use, trellis (default) or diamond")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq",
default=75e6,
help="System clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
toolchain=args.toolchain,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Cam Link 4K")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=81e6,
help="System clock frequency.")
target_group.add_argument("--toolchain",
default="trellis",
help="FPGA toolchain (trellis or diamond).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
toolchain=args.toolchain,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75E")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--revision", default="7.1", type=str, help="Board revision 7.1 (default)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default=60MHz)")
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(revision=args.revision,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
sys_clk_freq = args.sys_clk_freq,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on FPC-III")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
parser.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency (default=80MHz)")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Ethernet wishbone support")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq",
default=81e6,
help="System clock frequency (default: 81MHz)")
parser.add_argument("--toolchain",
default="trellis",
help="FPGA toolchain: trellis (default) or diamond")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
toolchain=args.toolchain,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Trellis Board")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_pmod_gpio = args.with_pmod_gpio,
**soc_core_argdict(args)
)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC on Colorlight 5A-75X")
parser.add_argument("--build",
action="store_true",
help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--board",
default="5a-75b",
help="Board type (5a-75b or 5a-75e).")
parser.add_argument("--revision",
default="7.0",
type=str,
help="Board revision (6.0, 6.1, 7.0 or 8.0).")
parser.add_argument("--sys-clk-freq",
default=60e6,
help="System clock frequency")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
parser.add_argument("--eth-ip",
default="192.168.1.50",
type=str,
help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-phy",
default=0,
type=int,
help="Ethernet PHY (0 or 1).")
parser.add_argument("--use-internal-osc",
action="store_true",
help="Use internal oscillator.")
parser.add_argument("--sdram-rate",
default="1:1",
help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(board=args.board,
revision=args.revision,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
eth_phy=args.eth_phy,
use_internal_osc=args.use_internal_osc,
sdram_rate=args.sdram_rate,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arctic Tern (BMC card carrier)")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
toolchain = args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC on Colorlight 5A-75B")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
parser.add_argument("--revision",
default="7.0",
type=str,
help="Board revision 7.0 (default) or 6.1")
parser.add_argument("--with-etherbone",
action="store_true",
help="enable Etherbone support")
parser.add_argument("--eth-phy",
default=0,
type=int,
help="Ethernet PHY 0 or 1 (default=0)")
parser.add_argument("--load", action="store_true", help="load bitstream")
args = parser.parse_args()
if args.load:
load()
if args.with_etherbone:
soc = EtherboneSoC(eth_phy=args.eth_phy,
revision=args.revision,
**soc_core_argdict(args))
else:
soc = BaseSoC(args.revision, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
args = parser.parse_args()
soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_core_argdict(args))
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument("--gateware-toolchain",
dest="toolchain",
default="trellis",
help='gateware toolchain to use, trellis (default)')
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq",
default=75e6,
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = {}
if args.toolchain == "trellis":
builder_kargs == trellis_argdict(args)
vns = builder.build(**builder_kargs)
csr_csv = export.get_csr_csv(soc.csr_regions, soc.constants)
write_to_file("test/csr.csv", csr_csv)
soc.analyzer.export_csv(
vns, "test/analyzer.csv") # Export the current analyzer configuration
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on FPC-III")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Hackaday Badge")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--toolchain",
default="trellis",
help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq",
default=48e6,
help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
parser.add_argument("--revision", default="0.2", help="Board Revision (0.1 or 0.2).")
parser.add_argument("--device", default="25F", help="ECP5 device (25F or 45F).")
parser.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
device = args.device,
sdram_device = args.sdram_device,
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75X")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--board", default="5a-75b", help="Board type: 5a-75b (default) or 5a-75e")
parser.add_argument("--revision", default="7.0", type=str, help="Board revision: 7.0 (default), 6.0 or 6.1")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1")
parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(board=args.board, revision=args.revision,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_phy = args.eth_phy,
use_internal_osc = args.use_internal_osc,
sdram_rate = args.sdram_rate,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Trellis Board")
parser.add_argument(
"--gateware-toolchain",
dest="toolchain",
default="trellis",
help="gateware toolchain to use, trellis (default) or diamond")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq",
default=75e6,
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--with-spi-sdcard",
action="store_true",
help="enable SPI-mode SDCard support")
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
**soc_sdram_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--device", default="LFE5UM5G", help="FPGA device (LFE5UM5G or LFE5UM).")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
device = args.device,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_phy = args.eth_phy,
toolchain = args.toolchain,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Logicbone")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)")
parser.add_argument("--device", default="45F", help="ECP5 device (default=45F)")
parser.add_argument("--sdram-device", default="MT41K512M16", help="ECP5 device (default=MT41K512M16)")
parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
parser.add_argument("--with-sdcard", action="store_true", help="enable SDCard support")
args = parser.parse_args()
soc = BaseSoC(
toolchain = args.toolchain,
device = args.device,
sdram_device = args.sdram_device,
with_ethernet = args.with_ethernet,
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args))
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument(
"--gateware-toolchain",
dest="toolchain",
default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq",
default=75e6,
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = {}
if args.toolchain == "trellis":
builder_kargs == trellis_argdict(args)
builder.build(**builder_kargs)
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC with PLL on Colorlight 5A-75B")
parser.add_argument("--revision",
action="store",
default="7.0",
help="Colorlight 5A-75B board revision (6.1 / 7.0)")
parser.add_argument("--cpu",
action="store",
default="vexriscv",
help="SoC CPU (vexriscv / picorv32)")
parser.add_argument("--freq",
action="store",
type=int,
default=50e6,
help="System clock frequency (Hz)")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(revision=args.revision, cpu=args.cpu, freq=args.freq)
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=True)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument(
"--toolchain",
default="trellis",
help="Gateware toolchain to use, trellis (default) or diamond")
parser.add_argument(
"--device",
dest="device",
default="LFE5U-45F",
help=
"FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F"
)
parser.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency (default=50MHz)")
parser.add_argument(
"--sdram-module",
default="MT48LC16M16",
help=
"SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)"
)
parser.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support")
parser.add_argument(
"--sdram-rate",
default="1:1",
help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(device=args.device,
toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
sdram_module_cls=args.sdram_module,
sdram_rate=args.sdram_rate,
**soc_sdram_argdict(args))
assert not (args.with_spi_sdcard and args.with_sdcard)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight i5")
parser.add_argument("--build",
action="store_true",
help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq",
default=60e6,
help="System clock frequency.")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
parser.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed).")
parser.add_argument("--use-internal-osc",
action="store_true",
help="Use internal oscillator.")
parser.add_argument("--sdram-rate",
default="1:1",
help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (HDMI).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
use_internal_osc=args.use_internal_osc,
sdram_rate=args.sdram_rate,
l2_size=args.l2_size,
with_spi_flash=args.with_spi_flash,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5")
parser.add_argument("--build",
action="store_true",
help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash",
action="store_true",
help="Flash bitstream to SPI Flash.")
parser.add_argument("--device",
default="85F",
help="ECP5 device (45F or 85F).")
parser.add_argument("--sys-clk-freq",
default=75e6,
help="System clock frequency.")
parser.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (HDMI).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(device=args.device,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
**soc_core_argdict(args))
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(None, builder.get_bitstream_filename(mode="flash"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
parser.add_argument("--device", default="LFE5U-45F", help="FPGA device: LFE5U-12F, LFE5U-25F, LFE5U-45F (default) or LFE5U-85F")
parser.add_argument("--revision", default="2.0", help="Board revision: 2.0 (default) or 1.7")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16 (default), AS4C32M16 or AS4C16M16")
parser.add_argument("--with-spiflash", action="store_true", help="Make the SPI Flash accessible from the SoC")
parser.add_argument("--flash-boot-adr", type=lambda x: int(x,0), default=None, help="Flash boot address")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--with-oled", action="store_true", help="Enable SDD1331 OLED support")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI)")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
device = args.device,
revision = args.revision,
toolchain = args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)),
sdram_module_cls = args.sdram_module,
sdram_rate = args.sdram_rate,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
spiflash = args.with_spiflash,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
if args.with_oled:
soc.add_oled()
if args.with_spiflash:
soc.add_spi_flash(mode="1x", dummy_cycles=8)
if args.flash_boot_adr:
soc.add_constant("FLASH_BOOT_ADDRESS", args.flash_boot_adr)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight i5")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--board", default="i5", help="Board type: i5 (default)")
parser.add_argument("--revision", default="7.0", type=str, help="Board revision: 7.0 (default)")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server")
parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1")
parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI)")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(board=args.board, revision=args.revision,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
local_ip = args.local_ip,
remote_ip = args.remote_ip,
eth_phy = args.eth_phy,
use_internal_osc = args.use_internal_osc,
sdram_rate = args.sdram_rate,
l2_size = args.l2_size,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
**soc_core_argdict(args)
)
soc.platform.add_extension(colorlight_i5._sdcard_pmod_io)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain",
default="trellis",
help="FPGA toolchain: trellis (default) or diamond")
parser.add_argument("--sys-clk-freq",
default=75e6,
help="System clock frequency (default: 75MHz)")
parser.add_argument("--device",
default="LFE5UM5G",
help="FPGA device (LFE5UM5G (default) or LFE5UM)")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
parser.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
parser.add_argument("--eth-ip",
default="192.168.1.50",
type=str,
help="Ethernet/Etherbone IP address")
parser.add_argument("--eth-phy",
default=0,
type=int,
help="Ethernet PHY: 0 (default) or 1")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
device=args.device,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
eth_phy=args.eth_phy,
toolchain=args.toolchain,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default=48MHz)")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ButterStick")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--revision", default="1.0", help="Board Revision (1.0).")
parser.add_argument("--device", default="85F", help="ECP5 device (25F, 45F, 85F).")
parser.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.")
parser.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-syzygy-gpio",action="store_true", help="Enable GPIOs through SYZYGY Breakout on Port-A.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
assert not (args.with_etherbone and args.eth_dynamic_ip)
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
device = args.device,
sdram_device = args.sdram_device,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
with_spi_flash = args.with_spi_flash,
with_syzygy_gpio = args.with_syzygy_gpio,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
