def generate_one(t):
print("Generating target:", t)
# Is it a simulation ?
is_sim = "sim" in t
# Muck with directory path
build_dir = make_new_dir(build_top_dir, t)
t_dir = make_new_dir(gen_dir, t)
cmd = ["litedram_gen", "--output-dir=%s" % build_dir]
if is_sim:
cmd.append("--sim")
cmd.append("%s.yml" % t)
subprocess.check_call(cmd)
# Grab generated gatewar dir
gw_dir = os.path.join(build_dir, "gateware")
# Generate init code
src_init_file = build_init_code(build_dir, is_sim)
src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
# Copy generated files to target dir, amend them if necessary
initfile_name = "litedram_core.init"
core_file = os.path.join(gw_dir, "litedram_core.v")
dst_init_file = os.path.join(t_dir, initfile_name)
dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl")
shutil.copyfile(src_init_file, dst_init_file)
shutil.copyfile(src_initram_file, dst_initram_file)
if is_sim:
initfile_path = os.path.join("litedram", "generated", "sim", initfile_name)
replace_in_file(dst_initram_file, initfile_name, initfile_path)
shutil.copy(core_file, t_dir)
def main():
parser = argparse.ArgumentParser(
description="LiteDRAM standalone core generator")
builder_args(parser)
parser.set_defaults(output_dir="build")
parser.add_argument("config", help="YAML config file")
parser.add_argument("--sim",
action='store_true',
help="Integrate SDRAMPHYModel in core for simulation")
args = parser.parse_args()
core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
# Convert YAML elements to Python/LiteX --------------------------------------------------------
for k, v in core_config.items():
replaces = {"False": False, "True": True, "None": None}
for r in replaces.keys():
if v == r:
core_config[k] = replaces[r]
if "clk_freq" in k:
core_config[k] = float(core_config[k])
if k == "sdram_module":
core_config[k] = getattr(litedram_modules, core_config[k])
if k == "sdram_phy":
core_config[k] = getattr(litedram_phys, core_config[k])
# Generate core --------------------------------------------------------------------------------
if args.sim:
platform = SimPlatform("", io=[])
elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
platform = LatticePlatform(
"LFE5UM5G-45F-8BG381C", io=[],
toolchain="trellis") # FIXME: allow other devices.
elif core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
platform = XilinxPlatform("", io=[], toolchain="vivado")
elif core_config["sdram_phy"] in [
litedram_phys.USDDRPHY, litedram_phys.USPDDRPHY
]:
platform = XilinxPlatform("", io=[], toolchain="vivado")
else:
raise ValueError("Unsupported SDRAM PHY: {}".format(
core_config["sdram_phy"]))
builder_arguments = builder_argdict(args)
builder_arguments["compile_gateware"] = False
soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000)
builder = Builder(soc, **builder_arguments)
builder.build(build_name="litedram_core", regular_comb=False)
if soc.cpu_type is not None:
init_filename = "mem.init"
os.system("mv {} {}".format(
os.path.join(builder.gateware_dir, init_filename),
os.path.join(builder.gateware_dir, "litedram_core.init"),
))
replace_in_file(os.path.join(builder.gateware_dir, "litedram_core.v"),
init_filename, "litedram_core.init")
def main():
parser = argparse.ArgumentParser(description="LiteX Bare Metal Demo App.")
parser.add_argument("--build-path", help="Target's build path (ex build/board_name).", required=True)
parser.add_argument("--with-cxx", action="store_true", help="Enable CXX support.")
parser.add_argument("--mem", default="main_ram", help="Memory Region where code will be loaded/executed.")
args = parser.parse_args()
# Create demo directory
os.makedirs("demo", exist_ok=True)
# Copy contents to demo directory
os.system(f"cp {os.path.abspath(os.path.dirname(__file__))}/* demo")
# Update memory region.
replace_in_file("demo/linker.ld", "main_ram", args.mem)
# Compile demo
build_path = args.build_path if os.path.isabs(args.build_path) else os.path.join("..", args.build_path)
os.system(f"export BUILD_DIR={build_path} && {'export WITH_CXX=1 &&' if args.with_cxx else ''} cd demo && make")
# Copy demo.bin
os.system("cp demo/demo.bin ./")
def apply_hyperram_integration_hack(self, v_file):
# FIXME: Gowin EDA expects a very specific HypeRAM integration pattern, modify generated verilog to match it.
# Convert to vectors.
tools.replace_in_file(v_file, "O_hpram_reset_n", "O_hpram_reset_n[0]")
tools.replace_in_file(v_file, "O_hpram_cs_n", "O_hpram_cs_n[0]")
tools.replace_in_file(v_file, "O_hpram_rwds", "O_hpram_rwds[0]")
tools.replace_in_file(v_file, "O_hpram_ck ", "O_hpram_ck[0] ")
tools.replace_in_file(v_file, "O_hpram_ck_n ", "O_hpram_ck_n[0] ")
tools.replace_in_file(v_file, "O_hpram_ck,", "O_hpram_ck[0],")
tools.replace_in_file(v_file, "O_hpram_ck_n,", "O_hpram_ck_n[0],")
tools.replace_in_file(v_file, "wire O_hpram_reset_n[0]",
"wire [0:0] O_hpram_reset_n")
tools.replace_in_file(v_file, "wire O_hpram_cs_n[0]",
"wire [0:0] O_hpram_cs_n")
tools.replace_in_file(v_file, "wire IO_hpram_rwds[0]",
"wire [0:0] IO_hpram_rwds")
tools.replace_in_file(v_file, "wire O_hpram_ck[0]",
"wire [0:0] O_hpram_ck")
tools.replace_in_file(v_file, "wire O_hpram_ck_n[0]",
"wire [0:0] O_hpram_ck_n")
# Apply Synthesis directives.
tools.replace_in_file(
v_file, "wire [0:0] IO_hpram_rwds,",
"wire [0:0] IO_hpram_rwds, /* synthesis syn_tristate = 1 */")
tools.replace_in_file(
v_file, "wire [7:0] IO_hpram_dq,",
"wire [7:0] IO_hpram_dq, /* synthesis syn_tristate = 1 */")
tools.replace_in_file(
v_file, "[1:0] IO_psram_rwds,",
"[1:0] IO_psram_rwds, /* synthesis syn_tristate = 1 */")
tools.replace_in_file(
v_file, "[15:0] IO_psram_dq,",
"[15:0] IO_psram_dq, /* synthesis syn_tristate = 1 */")
def generate_one(t, mw_init):
print("Generating target:", t)
# Muck with directory path
build_dir = make_new_dir(build_top_dir, t)
t_dir = make_new_dir(gen_dir, t)
# Grab config file
cfile = os.path.join(gen_src_dir, t + ".yml")
core_config = yaml.load(open(cfile).read(), Loader=yaml.Loader)
### TODO: Make most stuff below a function in litedram gen.py and
### call it rather than duplicate it
###
# Convert YAML elements to Python/LiteX
for k, v in core_config.items():
replaces = {"False": False, "True": True, "None": None}
for r in replaces.keys():
if v == r:
core_config[k] = replaces[r]
if "clk_freq" in k:
core_config[k] = float(core_config[k])
if k == "sdram_module":
core_config[k] = getattr(litedram_modules, core_config[k])
if k == "sdram_phy":
core_config[k] = getattr(litedram_phys, core_config[k])
# Override values for mw_init
if mw_init:
core_config["cpu"] = None
core_config["csr_expose"] = True
core_config["csr_align"] = 64
# Generate core
if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
platform = LatticePlatform("LFE5UM5G-45F-8BG381C",
io=[],
toolchain="trellis")
elif core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
platform = XilinxPlatform("", io=[], toolchain="vivado")
else:
raise ValueError("Unsupported SDRAM PHY: {}".format(
core_config["sdram_phy"]))
soc = LiteDRAMCore(platform,
core_config,
integrated_rom_size=0x6000,
csr_data_width=32)
# Build into build_dir
builder = Builder(soc, output_dir=build_dir, compile_gateware=False)
vns = builder.build(build_name="litedram_core", regular_comb=False)
# Grab generated gatewar dir
gw_dir = os.path.join(build_dir, "gateware")
# Generate init-cpu.txt if any and generate init code if none
cpu = core_config["cpu"]
if mw_init:
src_wrap_file = os.path.join(gen_src_dir, "wrapper-mw-init.vhdl")
src_init_file = build_init_code(build_dir)
else:
write_to_file(os.path.join(t_dir, "init-cpu.txt"), cpu)
src_wrap_file = os.path.join(gen_src_dir, "wrapper-self-init.vhdl")
src_init_file = os.path.join(gw_dir, "mem.init")
# Copy generated files to target dir, amend them if necessary
core_file = os.path.join(gw_dir, "litedram_core.v")
dst_init_file = os.path.join(t_dir, "litedram_core.init")
dst_wrap_file = os.path.join(t_dir, "litedram-wrapper.vhdl")
replace_in_file(core_file, "mem.init", "litedram_core.init")
shutil.copy(core_file, t_dir)
shutil.copyfile(src_init_file, dst_init_file)
shutil.copyfile(src_wrap_file, dst_wrap_file)
def generate_one(t):
print("Generating target:", t)
# Is it a simulation ?
is_sim = t is "sim"
# Muck with directory path
build_dir = make_new_dir(build_top_dir, t)
t_dir = make_new_dir(gen_dir, t)
# Grab config file
cfile = os.path.join(gen_src_dir, t + ".yml")
core_config = yaml.load(open(cfile).read(), Loader=yaml.Loader)
### TODO: Make most stuff below a function in litedram gen.py and
### call it rather than duplicate it
###
# Convert YAML elements to Python/LiteX
for k, v in core_config.items():
replaces = {"False": False, "True": True, "None": None}
for r in replaces.keys():
if v == r:
core_config[k] = replaces[r]
if "clk_freq" in k:
core_config[k] = float(core_config[k])
if k == "sdram_module":
core_config[k] = getattr(litedram_modules, core_config[k])
if k == "sdram_phy":
core_config[k] = getattr(litedram_phys, core_config[k])
# Generate core
if is_sim:
platform = SimPlatform("", io=[])
elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
platform = LatticePlatform("LFE5UM5G-45F-8BG381C",
io=[],
toolchain="trellis")
elif core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
platform = XilinxPlatform("", io=[], toolchain="vivado")
else:
raise ValueError("Unsupported SDRAM PHY: {}".format(
core_config["sdram_phy"]))
soc = LiteDRAMCore(platform,
core_config,
is_sim=is_sim,
integrated_rom_size=0x6000)
# Build into build_dir
builder = Builder(soc, output_dir=build_dir, compile_gateware=False)
vns = builder.build(build_name="litedram_core", regular_comb=False)
# Grab generated gatewar dir
gw_dir = os.path.join(build_dir, "gateware")
# Generate init code
src_init_file = build_init_code(build_dir, is_sim)
src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
# Copy generated files to target dir, amend them if necessary
initfile_name = "litedram_core.init"
core_file = os.path.join(gw_dir, "litedram_core.v")
dst_init_file = os.path.join(t_dir, initfile_name)
dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl")
shutil.copyfile(src_init_file, dst_init_file)
shutil.copyfile(src_initram_file, dst_initram_file)
if is_sim:
initfile_path = os.path.join("litedram", "generated", "sim",
initfile_name)
replace_in_file(dst_initram_file, initfile_name, initfile_path)
shutil.copy(core_file, t_dir)