def main(): args = sys.argv[1:] load = "load" in args build = (not "load" in args) if build: print("[building]...") plat = arty.Platform() plat.add_extension(_extension_io) module = Module() counter = Signal(32) module.sync += counter.eq(counter + 1) serial_pads = plat.request("serial") io_serial_pads = plat.request("io_serial") module.comb += [ serial_pads.tx.eq(io_serial_pads.rx), io_serial_pads.tx.eq(serial_pads.rx), plat.request("user_led", 0).eq(plat.request("io_leds", 0)), plat.request("user_led", 1).eq(plat.request("io_leds", 1)), plat.request("user_led", 2).eq(plat.request("io_leds", 2)), plat.request("io_rst", 0).eq(plat.request("user_btn", 0)), ] plat.build(module, source=False) elif load: print("[loading]...") prog = VivadoProgrammer() prog.load_bitstream("build/top.bit")
def main(): description = "LiteX-VexRiscv SoC Builder\n\n" parser = argparse.ArgumentParser( description=description, formatter_class=argparse.RawTextHelpFormatter) parser.add_argument("--build", action="store_true", help="build bitstream") parser.add_argument("--load", action="store_true", help="load bitstream (to SRAM)") parser.add_argument("--flash", action="store_true", help="flash bitstream/images (to SPI Flash)") args = parser.parse_args() if args.build: platform = basys3.Platform() dut = System(platform) platform.build(dut, build_dir="build/sys_accel_simulator_release/gateware") if args.load: from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream( "build/sys_accel_simulator_release/gateware/top.bit") if args.flash: from litex.build.openocd import OpenOCD prog = OpenOCD("../prog/openocd_xilinx.cfg", flash_proxy_basename="../prog/bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") prog.flash(0, "build/sys_accel_simulator_release/gateware/top.bin")
def main(): if "load" in sys.argv[1:]: from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream("build/gateware/kc705.bit") else: platform = kc705.Platform() soc = GTXTestSoC(platform) builder = Builder(soc, output_dir="build", compile_gateware=True) vns = builder.build(build_name="kc705")
def main(): args = sys.argv[1:] load = "load" in args build = not "load" in args if build: with_cpu = "cpu" in args with_emulator = "emulator" in args with_analyzer = "analyzer" in args print("[building]... cpu: {}, emulator: {}, analyzer: {}".format( with_cpu, with_emulator, with_analyzer)) soc = SDSoC(with_cpu, with_emulator, with_analyzer) builder = Builder(soc, output_dir="build", csr_csv="../test/csr.csv") vns = builder.build() soc.do_exit(vns) elif load: print("[loading]...") prog = VivadoProgrammer() prog.load_bitstream("build/gateware/top.bit")
def load(self): from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer(vivado_path=vivado_path) prog.load_bitstream("build/nexys_video/gateware/top.bit")
def load(): prog = VivadoProgrammer() prog.load_bitstream("build/gateware/kc705.bit")
#!/usr/bin/env python3 from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream(bitstream_file="build_pcie_cpri/gateware/top.bit")
#!/usr/bin/env python3 from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream(bitstream_file="build_kcu105/gateware/top.bit", target="localhost:3121/xilinx_tcf/Digilent/210308A0E6EA")
else: p = os.environ['PLATFORM'] t = os.environ['TARGET'] c = os.environ['CPU'] try: v = os.environ['CPU_VARIANT'] v = "." + v except: v = "" pass fname = "build/{p}_{t}_{c}{v}/gateware/top.bit".format(p=p, t=t, c=c, v=v) print("fname: ", fname) if prog == 'ise': from litex.build.xilinx import iMPACT prog = iMPACT() elif prog == 'vivado': from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() else: raise SystemError('Unknown programmer {}'.format(prog)) if not os.path.exists(fname): raise SystemError('File {} not found'.format(fname)) if not fname.endswith('.bit'): raise SystemError('Use the .bit file') prog.load_bitstream(fname)
def load_clkgen(): prog = VivadoProgrammer() prog.load_bitstream(bitstream_file="build_clkgen/gateware/top.bit")
def load_sayma_rtm(): prog = VivadoProgrammer() prog.load_bitstream(bitstream_file="build_sayma_rtm/gateware/top.bit", device=1)
def load_kcu105(): prog = VivadoProgrammer() prog.load_bitstream(bitstream_file="build_kcu105/gateware/top.bit")
#!/usr/bin/env python3 from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream(bitstream_file="build_kc705/gateware/top.bit", target="localhost:3121/xilinx_tcf/Digilent/210203336949A")
def load(): from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream("build/gateware/ac701.bit") exit()
#!/usr/bin/env python3 from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream( bitstream_file="build_pcie_radio/gateware/top.bit", target="localhost:3121/xilinx_tcf/Digilent/210249810959")
def load(): prog = VivadoProgrammer() prog.load_bitstream("build/gateware/top.bit") exit()
#!/usr/bin/env python3 from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream(bitstream_file="build_nexys/gateware/top.bit")
def load(self): from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream("build/daphne/gateware/top.bit")
#!/usr/bin/env python3 from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream("build/gateware/top.bit")