def finalize(self, fragment, *args, **kwargs): if self.finalized: raise ConstraintError("Already finalized") # if none exists, create a default clock domain and drive it if not fragment.clock_domains: if not hasattr(self, "default_clk_name"): raise NotImplementedError( "No default clock and no clock domain defined") crg = CRG(self.request(self.default_clk_name)) fragment += crg.get_fragment() self.do_finalize(fragment, *args, **kwargs) self.finalized = True
def finalize(self, fragment, *args, **kwargs): if self.finalized: raise ConstraintError("Already finalized") # if none exists, create a default clock domain and drive it if not fragment.clock_domains: if not hasattr(self, "default_clk_name"): raise NotImplementedError( "No default clock and no clock domain defined") crg = CRG(self.request(self.default_clk_name)) fragment += crg.get_fragment() self.do_finalize(fragment, *args, **kwargs) self.finalized = True
def __init__(self, platform): clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="LiteUSB example design", with_timer=False) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq) self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False) # Wishbone Bridge usb_bridge_port = self.usb_core.crossbar.get_port( self.usb_map["bridge"]) self.add_cpu_or_bridge( LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq)) self.add_wb_master(self.cpu_or_bridge.wishbone) # Leds leds = Cat(iter([platform.request("user_led", i) for i in range(8)])) self.submodules.leds = GPIOOut(leds)
def __init__(self, **kwargs): platform = sim.Platform() SoCSDRAM.__init__(self, platform, clk_freq=int((1 / (platform.default_clk_period)) * 1000000000), integrated_rom_size=0x8000, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) if not self.integrated_main_ram_size: sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings(memtype="SDR", dfi_databits=1 * 16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram(self.sdrphy, "minicon", sdram_module.geom_settings, sdram_module.timing_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024) self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024)
def __init__(self, platform): clk_freq = int((1/(platform.default_clk_period))*1000000000) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="Litescope example design", with_timer=False ) self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.io = LiteScopeIO(8) for i in range(8): try: self.comb += platform.request("user_led", i).eq(self.io.output[i]) except: pass counter = Signal(16) self.sync += counter.eq(counter + 1) toto = Signal() self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
def __init__(self, platform, **kwargs): SoCCore.__init__(self, platform, clk_freq=int( (1 / (platform.default_clk_period)) * 1000000000), integrated_rom_size=0x8000, integrated_main_ram_size=16 * 1024, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name))
def __init__(self, platform, firmware_ram_size=0x10000, firmware_filename=None, **kwargs): if not firmware_filename: firmware_filename = "build/sim_{}_{}/software/firmware/firmware.fbi".format( self.__class__.__name__.lower()[:-3], kwargs.get('cpu_type', 'lm32')) SoCSDRAM.__init__(self, platform, clk_freq=int((1 / (platform.default_clk_period)) * 1000000000), integrated_rom_size=0x8000, integrated_sram_size=0x8000, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM( firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.flash_boot_address = self.mem_map["firmware_ram"] # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings(memtype="SDR", dfi_databits=1 * 32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1)
def __init__(self, firmware_ram_size=0x10000, firmware_filename="firmware/firmware.bin", **kwargs): platform = sim.Platform() SoCSDRAM.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, integrated_sram_size=0x8000, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1) self.submodules.video_out = VideoOutCore(self.sdram.crossbar.get_port()) self.submodules.vga = VGAModel(platform.request("vga")) self.comb += self.video_out.source.connect(self.vga.sink)
def __init__(self, platform, clk_freq=166 * 1000000, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="LiteEth Base Design", with_timer=False) self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # wishbone SRAM (to test Wishbone over UART and Etherbone) self.submodules.sram = wishbone.SRAM(1024) self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus) # ethernet PHY and UDP/IP stack self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq) self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq) if isinstance(platform.toolchain, XilinxVivadoToolchain): self.specials += [ Keep(self.crg.cd_sys.clk), Keep(self.phy.crg.cd_eth_rx.clk), Keep(self.phy.crg.cd_eth_tx.clk) ] platform.add_platform_command(""" create_clock -name sys_clk -period 6.0 [get_nets sys_clk] create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk] create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk] set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk] set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk] """)
def __init__(self, platform): clk_freq = int(125e9) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="KCU105 1GHz Clock Generator", with_timer=False) self.submodules.crg = CRG(platform.request("clk125")) self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) pll_locked = Signal() pll_fb = Signal() pll_out = Signal() self.specials += [ Instance( "PLLE2_BASE", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, # VCO @ 1GHz p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0, p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, i_CLKIN1=ClockSignal(), i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, # 1GHz p_CLKOUT2_DIVIDE=1, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_out) ] user_sma_clock_pads = platform.request("user_sma_clock") self.specials += [ Instance("OBUFDS", i_I=pll_out, o_O=user_sma_clock_pads.p, o_OB=user_sma_clock_pads.n) ]
def __init__(self, platform): clk_freq = 125e6 self.submodules.crg = CRG(platform.request("clk125")) # amc amc_pll = SerdesPLL(125e6, 1e9) self.submodules += amc_pll self.comb += amc_pll.refclk.eq(ClockSignal()) self.submodules.amc_serdes = AMCMasterSerdes( amc_pll, platform.request("amc_serdes")) self.comb += self.amc_serdes.tx_data.eq(0x5a) self.submodules.amc_serdes_init = AMCMasterSerdesInit(self.amc_serdes) # rtm rtm_pll = SerdesPLL(125e6, 1e9) self.submodules += rtm_pll self.submodules.rtm_serdes = RTMSlaveSerdes( rtm_pll, platform.request("rtm_serdes")) self.comb += self.rtm_serdes.tx_data.eq(0x5a) self.submodules.rtm_serdes_init = RTMSlaveSerdesInit(self.rtm_serdes)