def __init__(self, pll):
platform = Platform()
sys_clk_freq = int(pll["refclk_freq"])
SoCCore.__init__(self,
platform,
cpu_type=None,
clk_freq=sys_clk_freq,
csr_data_width=32,
with_uart=False,
with_timer=False,
ident="Bit Error Ratio Analyzer",
ident_version=True)
# crg
self.submodules.crg = _CRG(platform, pll)
# No CPU, use Serial to control Wishbone bus
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# dna
self.submodules.dna = dna.DNA()
self.submodules.top_gtp = Top_gtp(self.crg.cd_sys.clk,
pll["refclk_freq"], pll["linerate"],
platform)
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="vexriscv",
clk_freq=100e6,
ident="LiteX CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
self.add_csr("switches")
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
self.add_csr("buttons")
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
self.add_csr("rgbled")
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"),
data_width=32,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=1e6)
self.add_csr("adxl362")
# SevenSegmentDisplay
self.submodules.display = SevenSegmentDisplay(sys_clk_freq)
self.add_csr("display")
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
l2_size=32,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="Arty DMA Test SoC",
ident_version=True,
reserve_nmi_interrupt=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(100e6))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
def __init__(self):
platform = Platform()
sys_clk_freq = int(100e6)
SoCCore.__init__(self,
platform,
cpu_type=None,
clk_freq=sys_clk_freq,
csr_data_width=32,
with_uart=False,
with_timer=False,
ident="TE014SoC Example Design",
ident_version=True)
# crg
self.submodules.crg = _CRG(platform)
# No CPU, use Serial to control Wishbone bus
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# dna
self.submodules.dna = dna.DNA()
self.submodules.top_gtp = Top_gtp(self.crg.cd_sys.clk, 100e6, 2e9,
platform)
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# lcd
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
self.submodules.rs = Led(platform.request("rs_lcd"))
self.submodules.rst = Led(platform.request("rst_lcd"))
def __init__(self, platform, **kwargs):
sys_clk_freq = int(12e6)
# SoC init
SoCCore.__init__(
self,
platform,
sys_clk_freq,
# cpu_type="picorv32",
# cpu_type="vexriscv",
cpu_type="lm32",
csr_data_width=32,
# shadow_base=0x00000000,
integrated_rom_size=32768,
integrated_main_ram_size=16384,
# with_uart=True,
ident="Test Proj",
ident_version=True,
# reserve_nmi_interrupt=True,
# with_timer=True,
# with_ctrl=True
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk12"),
platform.request("user_btn"))
# FPGA identification
self.submodules.dna = dna.DNA()
# wb leds
user_leds = Cat(*[platform.request("user_led") for i in range(2)])
self.submodules.wb_leds = wb_leds.WB_LEDS(platform, user_leds)
self.add_wb_slave(mem_decoder(self.mem_map["wb_leds"]),
self.wb_leds.wishbone)
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoC init (No CPU, we controlling the SoC with UART)
SoCCore.__init__(
self,
platform,
sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
ident="BER Analyser Arty",
ident_version=True,
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"))
# No CPU, use Serial to control Wishbone bus
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
self.submodules.top = Top()
def __init__(self, **kwargs):
print("hello_ETH BaseSoc: ", kwargs)
SoCCore.__init__(
self,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
integrated_rom_size=0,
integrated_main_ram_size=0,
# integrated_sram_size=0,
ident="SP605 eth demo",
ident_version=True,
**kwargs)
# Serial to Wishbone bridge
self.add_cpu(
uart.UARTWishboneBridge(self.platform.request("serial"),
self.clk_freq,
baudrate=1152000))
self.add_wb_master(self.cpu.wishbone)
# Clock Reset Generation
self.submodules.crg = _CRG(self.platform, self.clk_freq)
# FPGA identification
self.submodules.dna = dna.DNA()
def __init__(self, sys_clk_freq=int(62.5e6), **kwargs):
platform = daphne.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DNA --------------------------------------------------------------------------------------
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# XADC -------------------------------------------------------------------------------------
# self.submodules.xadc = xadc.XADC()
# self.add_csr("xadc")
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR2",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT47H128M8(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self, clk_freq, sample_tx_freq, **kwargs):
print("HelloLtc: ", kwargs)
SoCCore.__init__(
self,
clk_freq=clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
integrated_rom_size=0,
integrated_main_ram_size=0,
integrated_sram_size=0,
ident="LTC2175 demonstrator", ident_version=True,
**kwargs
)
p = self.platform
self.submodules.crg = _CRG(p, clk_freq, sample_tx_freq)
# ----------------------------
# Serial to Wishbone bridge
# ----------------------------
self.add_cpu(uart.UARTWishboneBridge(
p.request("serial"),
clk_freq,
baudrate=1152000
))
self.add_wb_master(self.cpu.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
# ----------------------------
# FMC LPC connectivity & LTC LVDS driver
# ----------------------------
# LTCPhy will recover ADC clock and drive `sample` clock domain
p.add_extension(ltc_pads)
self.submodules.lvds = LTCPhy(p, sample_tx_freq)
# ----------------------------
# SPI master
# ----------------------------
spi_pads = p.request("LTC_SPI")
self.submodules.spi = spi.SPIMaster(spi_pads)
# ----------------------------
# Acquisition memory for ADC data
# ----------------------------
mem = Memory(16, 4096)
self.specials += mem
self.submodules.sample_ram = SRAM(mem, read_only=True)
self.register_mem("sample", 0x50000000, self.sample_ram.bus, 4096)
self.submodules.acq = Acquisition([mem])
self.specials += MultiReg(
p.request("user_btn"), self.acq.trigger
)
self.comb += [
p.request("user_led").eq(self.acq.busy),
self.acq.data_ins[0].eq(self.lvds.sample_out),
]
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoC init (No CPU, we controlling the SoC with UART)
SoCCore.__init__(
self,
platform,
sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
ident="My first System On Chip",
ident_version=True,
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# No CPU, use Serial to control Wishbone bus
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoCMini (No CPU, we are controlling the SoC over UART)
SoCMini.__init__(self, platform, sys_clk_freq, csr_data_width=32,
ident="My first LiteX System On Chip", ident_version=True)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset"))
# No CPU, use Serial to control Wishbone bus
self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
self.add_wb_master(self.serial_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
# Switches
user_switches = Cat(*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
self.add_csr("switches")
# Buttons
user_buttons = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
self.add_csr("buttons")
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
self.add_csr("rgbled")
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"),
data_width = 32,
sys_clk_freq = sys_clk_freq,
spi_clk_freq = 1e6)
self.add_csr("adxl362")
# SevenSegmentDisplay
self.submodules.display = SevenSegmentDisplay(sys_clk_freq)
self.add_csr("display")
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform):
sys_clk_freq = int(100e6)
SoCCore.__init__(
self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024,
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
# SD
self.submodules.SD = SD(platform.request("SD"),
platform.request("butt"), "csr")
# LCD
self.submodules.LCD = SPIMaster(platform.request("LCD"))
def __init__(self, platform, target_name, analog_pads=None):
self.submodules.dna = dna.DNA()
self.submodules.git = git.GitInfo()
target = target_name.lower()[:-3]
self.submodules.platform = platform_info.PlatformInfo(
platform.name, target)
if "xc7" in platform.device:
self.submodules.xadc = xadc.XADC(analog_pads)
if analog_pads != None:
self.xadc.expose_drp()
def __init__(self, platform, **kwargs):
sys_clk_freq = int(1 / platform.default_clk_period * 1000000000)
SoCCore.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv",
# cpu_variant="debug",
# cpu_type="picorv32",
# cpu_type="lm32",
csr_data_width=32,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024,
ident="Wir trampeln durchs Getreide ...",
ident_version=True)
for c in [
"dna",
"xadc",
"rgbled",
"leds",
# "switches",
"buttons"
# "adxl362",
# "display"
]:
self.add_csr(c)
# self.submodules.bridge = uart.UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
# self.add_wb_master(self.bridge.wishbone)
# self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu_or_bridge.debug_bus, 0x10)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk12"),
platform.request("user_btn"))
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led") for i in range(2)])
self.submodules.leds = Led(user_leds)
# Buttons
user_buttons = Cat(*[platform.request("user_btn") for i in range(1)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("rgb_leds"))
def __init__(self, platform):
sys_clk_freq = int(100e6)
SoCCore.__init__(
self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024,
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
# LCD parallel
self.submodules.lcd_test = LCD_i80()
self.comb += [
platform.request("db").eq(self.lcd_test.db_),
platform.request("cs").eq(self.lcd_test.cs_),
platform.request("rs").eq(self.lcd_test.rs_),
platform.request("rd").eq(self.lcd_test.rd_),
platform.request("wr").eq(self.lcd_test.wr_),
platform.request("rst").eq(self.lcd_test.rst_),
platform.request("dba").eq(self.lcd_test.db_),
platform.request("csa").eq(self.lcd_test.cs_),
platform.request("rsa").eq(self.lcd_test.rs_),
platform.request("rda").eq(self.lcd_test.rd_),
platform.request("wra").eq(self.lcd_test.wr_),
platform.request("rsta").eq(self.lcd_test.rst_),
platform.request("busy").eq(self.lcd_test.BUSY.status)
]
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
interrupt_map = {
"buttons": 4,
}
SoCCore.interrupt_map.update(interrupt_map)
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=32 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(8)])
self.submodules.buttons = btnintrupt(user_buttons)
#LedAzul
user_led = Cat(*[platform.request("led_GB", i) for i in range(1)])
self.submodules.led_GB = Led(user_led)
#spiLCD
user_control = Cat(
*[platform.request("pantalla_control", i) for i in range(3)])
self.submodules.pantalla_spi = SPIMaster(
platform.request("pantalla_spi"))
self.submodules.pantalla_control = Led(user_control)
#spiSd
user_control_sd = Cat(
*[platform.request("sdcard_v", i) for i in range(1)])
self.submodules.sdcard_spi = SPIMaster(platform.request("sdcard_spi"))
self.submodules.sdcard_v = Led(user_control_sd)
print(SoCCore.interrupt_map)
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="NeTV2 LiteX Base SoC",
reserve_nmi_interrupt=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(100e6))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# common led
self.sys_led = Signal()
self.pcie_led = Signal()
self.comb += platform.request("user_led",
0).eq(self.sys_led ^ self.pcie_led)
# sys led
sys_counter = Signal(32)
self.sync += sys_counter.eq(sys_counter + 1)
self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, sys_clk_freq=int(83333333), **kwargs):
platform = Platform()
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="Alchitry Au SoC",
ident_version=True,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=AS4C128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x10000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# No CPU, use Serial to control Wishbone bus
#self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
#self.add_wb_master(self.serial_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(8)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(66666666), **kwargs):
platform = Platform()
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="Mojo V3 SoC",
ident_version=True,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
#self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.submodules.sdrphy = HalfRateGENSDRPHY(
platform.request("sdram"))
self.add_sdram(
"sdram",
phy=self.sdrphy,
#module = MT48LC32M8(sys_clk_freq, "1:1"),
module=MT48LC32M8(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x2000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get("min_l2_data_width", 128),
l2_cache_reverse=True)
# No CPU, use Serial to control Wishbone bus
#self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
#self.add_wb_master(self.serial_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(8)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
def __init__(self, platform, **kwargs):
sys_clk_freq = platform.clkFreq
# SoCMini (No CPU, we are controlling the SoC over UART)
SoCMini.__init__(self,
platform,
sys_clk_freq,
csr_data_width=32,
ident="My first LiteX System On Chip",
ident_version=True)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk29"))
# No CPU, use Serial to control Wishbone bus
self.submodules.serial_bridge = UARTWishboneBridge(
platform.request("uart"), sys_clk_freq)
self.add_wb_master(self.serial_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# Led
self.submodules.led = GPIOOut(
Cat([
platform.request("green_led"),
platform.request("orange_led")
]))
self.add_csr("led")
# Display 7 Segments
self.submodules.display7Seg = SevenSegmentDisplay(
sys_clk_freq, platform.request("seven_seg"))
self.add_csr("display7Seg")
# Encoder
self.submodules.encoder = RotaryEncoder(sys_clk_freq,
platform.request("encoder"))
self.add_csr("encoder")
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self, platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC", ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16*1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# lcd
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
self.submodules.rs = Led(platform.request("rs_lcd"))
self.submodules.rst = Led(platform.request("rst_lcd"))
#sdcard
#self.submodules.sdcard = SDCore(platform.request("sd_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCCore.__init__(self, platform, clk_freq,
integrated_rom_size=0x6000,
integrated_sram_size=0x4000,
ident="NeTV2 minimum SoC core",
reserve_nmi_interrupt=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6))
# common led
self.sys_led = Signal()
self.comb += platform.request("user_led", 0).eq(self.sys_led)
# sys led
sys_counter = Signal(32)
self.sync += sys_counter.eq(sys_counter + 1)
self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
csr_data_width=32,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=35 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
#RS y RST LCD
rs = platform.request("lcd_rs")
self.submodules.rs = Led(rs)
rst = platform.request("lcd_rst")
rst = 1
# Buttons
bttn = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = button_intr(bttn)
#GPO
self.submodules.GPO = Led(platform.request("GPO", 0))
#SD
self.submodules.SD = SPIMaster(platform.request("SD_spi"))
# LCD
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoCCore --------------------_-------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Nereid",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DNA --------------------------------------------------------------------------------------
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# XADC -------------------------------------------------------------------------------------
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8KTF51264(sys_clk_freq,
"1:4",
speedgrade="800"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# PCIe -------------------------------------------------------------------------------------
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
bar0_size=0x20000)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(
self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma
self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma")
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.msis = {
"DMA_WRITER": self.pcie_dma.writer.irq,
"DMA_READER": self.pcie_dma.reader.irq
}
for i, (k, v) in enumerate(sorted(self.msis.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, with_pcie_uart=True):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
csr_data_width=32,
integrated_rom_size=0x10000,
integrated_sram_size=0x10000,
integrated_main_ram_size=
0x10000, # FIXME: keep this for initial PCIe tests
ident="Tagus LiteX Test SoC",
ident_version=True,
with_uart=not with_pcie_uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DNA --------------------------------------------------------------------------------------
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# XADC -------------------------------------------------------------------------------------
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_csr("ddrphy")
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# PCIe -------------------------------------------------------------------------------------
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
bar0_size=0x20000)
self.pcie_phy.cd_pcie.clk.attr.add("keep")
platform.add_platform_command(
"create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(
self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma
self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma")
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.msis = {
"DMA_WRITER": self.pcie_dma.writer.irq,
"DMA_READER": self.pcie_dma.reader.irq
}
for i, (k, v) in enumerate(sorted(self.msis.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# pcie_uart
if with_pcie_uart:
class PCIeUART(Module, AutoCSR):
def __init__(self, uart):
self.rx_valid = CSRStatus()
self.rx_ready = CSR()
self.rx_data = CSRStatus(8)
self.tx_valid = CSR()
self.tx_ready = CSRStatus()
self.tx_data = CSRStorage(8)
# # #
# cpu to pcie
self.comb += [
self.rx_valid.status.eq(uart.sink.valid),
uart.sink.ready.eq(self.rx_ready.re),
self.rx_data.status.eq(uart.sink.data),
]
# pcie to cpu
self.sync += [
If(self.tx_valid.re, uart.source.valid.eq(1)).Elif(
uart.source.ready, uart.source.valid.eq(0))
]
self.comb += [
self.tx_ready.status.eq(~uart.source.valid),
uart.source.data.eq(self.tx_data.storage)
]
uart_interface = RS232PHYInterface()
self.submodules.uart = UART(uart_interface)
self.add_csr("uart")
self.add_interrupt("uart")
self.submodules.pcie_uart = PCIeUART(uart_interface)
self.add_csr("pcie_uart")
# Leds -------------------------------------------------------------------------------------
# led blinking (sys)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += [
platform.request("user_led", 0).eq(1),
platform.request("user_led", 1).eq(sys_counter[26]),
platform.request("user_led", 2).eq(1),
]
def __init__(self, platform, **kwargs):
# TODO Fix the spi flash write speed in bitbang mode
#sys_clk_freq = 100.295 * 1000000
sys_clk_freq = 29.498 * 1000000
SoCCore.mem_map = {
"rom": 0x00000000,
"sram": 0x01000000,
"main_ram": 0x40000000,
"spiflash": 0x60000000,
"csr": 0x82000000,
}
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="vexriscv",
clk_freq=sys_clk_freq,
ident="LiteX CPU Test SoC",
ident_version=True,
integrated_rom_size=0x4000,
integrated_main_ram_size=0x2000,
uart_name="uart")
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk29"),
~platform.request("buttons")[3])
#self.submodules.crg = _CRG(platform, sys_clk_freq)
#self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# SPI Flash
self.submodules.spiflash = SpiFlash(platform.request("spiflash"),
dummy=8,
div=4,
endianness="little")
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=2 * mB)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 4096)
self.add_constant("FLASH_BOOT_ADDRESS",
self.mem_map['spiflash'] + 0x100000)
# Led
self.submodules.led = GPIOOut(
Cat([
platform.request("green_led"),
platform.request("orange_led")
]))
self.add_csr("led")
# Display 7 Segments
self.submodules.display7Seg = SevenSegmentDisplay(
sys_clk_freq, platform.request("seven_seg"))
self.add_csr("display7Seg")
# Encoder
self.submodules.encoder = RotaryEncoder(sys_clk_freq,
platform.request("encoder"))
self.add_csr("encoder")
# ST7565 Display
# TODO usar o modulo spi.py do LiteX para controlar o display pela CPU
displayPins = platform.request("spi_display")
self.submodules.display = St7565Display(sys_clk_freq, displayPins)
self.add_csr("display")
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Tagus",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DNA --------------------------------------------------------------------------------------
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# XADC -------------------------------------------------------------------------------------
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_csr("ddrphy")
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# PCIe -------------------------------------------------------------------------------------
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
bar0_size=0x20000)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(
self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma
self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma")
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.msis = {
"DMA_WRITER": self.pcie_dma.writer.irq,
"DMA_READER": self.pcie_dma.reader.irq
}
for i, (k, v) in enumerate(sorted(self.msis.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
def __init__(self,
platform,
with_sdram_bist=True,
bist_async=True,
bist_random=True,
spiflash="spiflash_1x",
**kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
with_uart=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
uart_interfaces = [RS232PHYInterface() for i in range(2)]
self.submodules.uart = UART(uart_interfaces[0])
self.submodules.bridge = WishboneStreamingBridge(
uart_interfaces[1], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
self.submodules.uart_phy = RS232PHY(platform.request("serial"),
self.clk_freq, 115200)
self.submodules.uart_multiplexer = UARTMultiplexer(
uart_interfaces, self.uart_phy)
self.comb += self.uart_multiplexer.sel.eq(
platform.request("user_sw", 0))
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(100e6))
self.submodules.leds = led.ClassicLed(
Cat(platform.request("user_led", i) for i in range(4)))
self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 3)
self.add_constant("A7DDRPHY_DELAY", 14)
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(
self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(cmd_buffer_depth=8))
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(
mode="write", cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(
generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(
mode="read", cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port,
random=bist_random)
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
16 * 1024 * 1024)
def __init__(self, platform,
with_sdram=True,
with_ethernet=False,
with_etherbone=True,
with_sdcard=True,
with_pcie=False,
with_hdmi_in0=False, with_hdmi_out0=False,
with_hdmi_in1=False, with_hdmi_out1=False,
with_interboard_communication=False):
assert not (with_pcie and with_interboard_communication)
sys_clk_freq = int(100e6)
sd_freq = int(100e6)
SoCSDRAM.__init__(self, platform, sys_clk_freq,
#cpu_type="vexriscv", l2_size=32,
cpu_type=None, l2_size=32,
#csr_data_width=8, csr_address_width=14,
csr_data_width=32, csr_address_width=14,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
integrated_main_ram_size=0x8000 if not with_sdram else 0,
ident="NeTV2 LiteX Test SoC", ident_version=True,
reserve_nmi_interrupt=False)
# crg
self.submodules.crg = CRG(platform, sys_clk_freq)
# dnax
self.submodules.dna = dna.DNA()
# xadc
self.submodules.xadc = xadc.XADC()
# icap
self.submodules.icap = ICAP(platform)
# flash
self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6))
# sdram
if with_sdram:
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6)
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# ethernet
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# etherbone
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq)
self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master"))
self.add_wb_master(self.cpu.wishbone.bus)
#self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
#self.add_wb_master(self.etherbone.wishbone.bus)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# sdcard
self.submodules.sdclk = SDClockerS7()
self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device)
self.submodules.sdcore = SDCore(self.sdphy)
self.submodules.sdtimer = Timer()
self.submodules.bist_generator = BISTBlockGenerator(random=True)
self.submodules.bist_checker = BISTBlockChecker(random=True)
self.comb += [
self.sdcore.source.connect(self.bist_checker.sink),
self.bist_generator.source.connect(self.sdcore.sink)
]
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq)
self.crg.cd_sys.clk.attr.add("keep")
self.sdclk.cd_sd.clk.attr.add("keep")
self.sdclk.cd_sd_fb.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.sdclk.cd_sd.clk,
self.sdclk.cd_sd_fb.clk)
# pcie
if with_pcie:
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2"))
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True)
# pcie wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000)
self.add_wb_master(self.pcie_bridge.wishbone)
# pcie dma
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# interboard communication
if with_interboard_communication:
self.clock_domains.cd_refclk = ClockDomain()
self.submodules.refclk_pll = refclk_pll = S7PLL()
refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6)
refclk_pll.create_clkout(self.cd_refclk, 125e6)
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# qpll
qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9)
print(qpll)
self.submodules += qpll
# gtp
gtp = GTP(qpll,
platform.request("interboard_comm_tx"),
platform.request("interboard_comm_rx"),
sys_clk_freq,
clock_aligner=True, internal_loopback=False)
self.submodules += gtp
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)
# send counter to other-board
self.comb += [
gtp.encoder.k[0].eq(1),
gtp.encoder.d[0].eq((5 << 5) | 28),
gtp.encoder.k[1].eq(0),
gtp.encoder.d[1].eq(counter[26:])
]
# receive counter and display it on leds
self.comb += [
platform.request("user_led", 3).eq(gtp.rx_ready),
platform.request("user_led", 4).eq(gtp.decoders[1].d[0]),
platform.request("user_led", 5).eq(gtp.decoders[1].d[1])
]
gtp.cd_tx.clk.attr.add("keep")
gtp.cd_rx.clk.attr.add("keep")
platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.cd_tx.clk,
gtp.cd_rx.clk)
# hdmi in 0
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk),
for clk in [self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6))
# hdmi out 0
if with_hdmi_out0:
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
platform.request("hdmi_out", 0),
hdmi_out0_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# hdmi in 1
if with_hdmi_in1:
hdmi_in1_pads = platform.request("hdmi_in", 1)
self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in1 = HDMIIn(
hdmi_in1_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk),
for clk in [self.hdmi_in1.clocking.cd_pix.clk,
self.hdmi_in1.clocking.cd_pix1p25x.clk,
self.hdmi_in1.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6))
# hdmi out 1
if with_hdmi_out1:
hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True)
self.submodules.hdmi_out1 = VideoOut(
platform.device,
platform.request("hdmi_out", 1),
hdmi_out1_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# led blinking (sys)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# led blinking (pcie)
if with_pcie:
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# led blinking (sdcard)
if with_sdcard:
sd_counter = Signal(32)
self.sync.sd += sd_counter.eq(sd_counter + 1)
self.comb += platform.request("user_led", 1).eq(sd_counter[26])
