def add_uart(self, name, baudrate=115200):
from litex.soc.cores import uart
if name in ["stub", "stream"]:
self.submodules.uart = uart.UART()
if name == "stub":
self.comb += self.uart.sink.ready.eq(1)
elif name == "bridge":
self.submodules.uart = uart.UARTWishboneBridge(
pads = self.platform.request("serial"),
clk_freq = self.sys_clk_freq,
baudrate = baudrate)
self.bus.add_master(name="uart_bridge", master=self.uart.wishbone)
elif name == "crossover":
self.submodules.uart = uart.UARTCrossover()
else:
if name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
elif name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=self.platform.device)
else:
self.submodules.uart_phy = uart.UARTPHY(
pads = self.platform.request(name),
clk_freq = self.sys_clk_freq,
baudrate = baudrate)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.csr.add("uart_phy", use_loc_if_exists=True)
self.csr.add("uart", use_loc_if_exists=True)
self.irq.add("uart", use_loc_if_exists=True)
def __init__(self, sys_clk_freq=int(100e6)):
platform = nexys4.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv", # or picorv32
ident="LiteX SoC on Nexys4",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000,
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
# Uart Adicional
# Classical UART. En /litex/soc/integration/soc.py
self.submodules.uart1_phy = uart.UARTPHY(
pads=platform.request("uart1"),
clk_freq=self.sys_clk_freq,
baudrate=9600
) # crea un objeto uart RS232PHY. Este despues se pasa a UART
self.submodules.uart1 = ResetInserter()(
uart.UART(
self.uart1_phy, #paso a UART. ResetInserter no idea
tx_fifo_depth=16,
rx_fifo_depth=16))
self.csr.add("uart1_phy", use_loc_if_exists=True)
self.csr.add("uart1", use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"):
self.irq.add("uart1", use_loc_if_exists=True)
else:
self.add_constant("UART_POLLING")
def __init__(
self,
platform,
clk_freq,
# CPU parameters
cpu_type="vexriscv",
cpu_reset_address=0x00000000,
cpu_variant=None,
# ROM parameters
integrated_rom_size=0,
integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=4096,
integrated_sram_init=[],
# MAIN_RAM parameters
integrated_main_ram_size=0,
integrated_main_ram_init=[],
# CSR parameters
csr_data_width=8,
csr_alignment=32,
csr_address_width=14,
# Identifier parameters
ident="",
ident_version=False,
# UART parameters
with_uart=True,
uart_name="serial",
uart_baudrate=115200,
uart_stub=False,
# Timer parameters
with_timer=True,
# Controller parameters
with_ctrl=True,
# Wishbone parameters
with_wishbone=True,
wishbone_timeout_cycles=1e6,
**kwargs):
self.platform = platform
self.clk_freq = clk_freq
# SoC's CSR/Mem/Interrupt mapping (default or user defined + dynamically allocateds)
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
self.soc_io_regions = self.io_regions
# SoC's Config/Constants/Regions
self.config = {}
self.constants = {}
self.mem_regions = {}
self.csr_regions = {}
# Wishbone masters/slaves lists
self._wb_masters = []
self._wb_slaves = []
# CSR masters list
self._csr_masters = []
self.add_retro_compat(kwargs)
# Parameters managment ---------------------------------------------------------------------
if cpu_type == "None":
cpu_type = None
if not with_wishbone:
self.soc_mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 32, 64]
assert 2**(csr_address_width + 2) <= 0x1000000
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------
# Add user's CSRs (needs to be done before the first dynamic allocation)
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
# Add SoCController
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
# Add CPU
self.config["CPU_TYPE"] = str(cpu_type).upper()
if cpu_type is not None:
if cpu_variant is not None:
self.config["CPU_VARIANT"] = str(
cpu_variant.split('+')[0]).upper()
# Check type
if cpu_type not in cpu.CPUS.keys():
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
# Add the CPU
self.add_cpu(cpu.CPUS[cpu_type](platform, self.cpu_variant))
# Update Memory Map (if defined by CPU)
self.soc_mem_map.update(self.cpu.mem_map)
# Update IO Regions (if defined by CPU)
self.soc_io_regions.update(self.cpu.io_regions)
# Set reset address
self.cpu.set_reset_address(
self.soc_mem_map["rom"]
if integrated_rom_size else cpu_reset_address)
self.config["CPU_RESET_ADDR"] = self.cpu.reset_address
# Add CPU buses as 32-bit Wishbone masters
for cpu_bus in self.cpu.buses:
assert cpu_bus.data_width in [32, 64, 128]
soc_bus = wishbone.Interface(data_width=32)
self.submodules += wishbone.Converter(cpu_bus, soc_bus)
self.add_wb_master(soc_bus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", allow_user_defined=True)
# Add CPU interrupts
for _name, _id in self.cpu.interrupts.items():
self.add_interrupt(_name, _id)
# Allow SoCController to reset the CPU
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
else:
self.add_cpu(cpu.CPUNone())
self.soc_io_regions.update(self.cpu.io_regions)
# Add user's interrupts (needs to be done after CPU interrupts are allocated)
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
# Add integrated ROM
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True,
init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size,
init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(
integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
# Add UART
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
if uart_name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
elif uart_name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=platform.device)
else:
self.submodules.uart_phy = uart.UARTPHY(
platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(
self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + get_version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
# Add Timer
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
# Add Wishbone to CSR bridge
csr_alignment = max(csr_alignment, self.cpu.data_width)
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.config["CSR_ALIGNMENT"] = csr_alignment
self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
if with_wishbone:
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(address_width=csr_address_width,
data_width=csr_data_width))
self.add_csr_master(self.wishbone2csr.csr)
self.register_mem("csr", self.soc_mem_map["csr"],
self.wishbone2csr.wishbone, 0x1000000)
def __init__(self,
platform,
use_dsp=False,
placer="heap",
output_dir="build",
pnr_seed=0,
sim=False,
hard_i2c=False,
**kwargs):
self.output_dir = output_dir
# Core -------------------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq,
integrated_sram_size=0,
with_uart=False,
cpu_reset_address=self.mem_map["spiflash"] +
GATEWARE_SIZE,
csr_data_width=32,
**kwargs)
self.cpu.use_external_variant(
"deps/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_MinPlus.v"
)
self.submodules.crg = platform.CRG(platform)
self.add_csr("crg")
# Version ----------------------------------------------------------------------------------------
self.submodules.git = GitInfo()
self.add_csr("git")
# Power management -------------------------------------------------------------------------------
# Betrusted Power management interface
self.submodules.power = BtPower(platform.request("power"))
self.add_csr("power")
# Keyboard power-on + debug mux ------------------------------------------------------------------
# Use to debug bootstrapping issues, avoid internal state on SoC messing with access to UART pads.
# Prevents sleep/wake from working due to loss of modal pinmux.
debugonly = False
if debugonly:
self.submodules.uart_phy = uart.UARTPHY(
pads=platform.request("serial"),
clk_freq=clk_freq,
baudrate=115200)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
tx_fifo_depth=256,
rx_fifo_depth=16))
self.add_csr("uart_phy")
self.add_csr("uart")
self.add_interrupt("uart")
else:
serialpads = platform.request("serial")
dbguart_tx = Signal()
dbguart_rx = Signal()
dbgpads = Record([('rx', 1), ('tx', 1)], name="serial")
dbgpads.rx = dbguart_rx
dbgpads.tx = dbguart_tx
# serialpad RX needs to drive a scan signal so we can detect it on the other side of the matrix
keycol0_ts = TSTriple(1)
self.specials += keycol0_ts.get_tristate(serialpads.rx)
#self.comb += serialpads.rx.eq(1)
self.comb += dbgpads.rx.eq(keycol0_ts.i)
self.comb += self.power.mon1.eq(platform.request("up5k_keyrow1"))
self.comb += self.power.mon0.eq(platform.request("up5k_keyrow0"))
# serialpad TX is what we use to test for keyboard hit to power on the SOC
# only allow test keyboard hit patterns when the SOC is powered off
self.comb += [
If(self.power.stats.fields.state, serialpads.tx.eq(dbgpads.tx),
keycol0_ts.oe.eq(0)).Else(
serialpads.tx.eq(self.power.power.fields.kbddrive),
keycol0_ts.oe.eq(1))
]
self.comb += keycol0_ts.o.eq(1) # drive a '1' for scan
# Uart block ------------------------------------------------------------------------------------
self.submodules.uart_phy = uart.UARTPHY(pads=dbgpads,
clk_freq=clk_freq,
baudrate=115200)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
tx_fifo_depth=256,
rx_fifo_depth=16))
self.add_csr("uart_phy")
self.add_csr("uart")
self.add_interrupt("uart")
# RAM/ROM/reset cluster --------------------------------------------------------------------------
spram_size = 128 * 1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
spram_size)
# Add a simple bit-banged SPI Flash module
spi_pads = platform.request("spiflash")
self.submodules.picorvspi = PicoRVSpi(platform, spi_pads)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.picorvspi.bus,
size=SPI_FLASH_SIZE)
self.add_csr("picorvspi")
# I2C --------------------------------------------------------------------------------------------
if hard_i2c:
self.submodules.i2c = HardI2C(platform, platform.request("i2c", 0))
self.add_wb_slave(self.mem_map["i2c"], self.i2c.bus, 16 * 4)
self.add_memory_region("i2c",
self.mem_map["i2c"],
16 * 4,
type='io')
self.add_csr("i2c")
self.add_interrupt("i2c")
else:
self.submodules.i2c = RtlI2C(platform, platform.request("i2c", 0))
self.add_csr("i2c")
self.add_interrupt("i2c")
# High-resolution tick timer ---------------------------------------------------------------------
self.submodules.ticktimer = TickTimer(1000, clk_freq, bits=40)
self.add_csr("ticktimer")
self.add_interrupt("ticktimer")
# COM port (spi peripheral to Artix) ------------------------------------------------------------------
self.submodules.com = SpiFifoPeripheral(platform.request("com"),
pipeline_cipo=True)
self.add_wb_slave(self.mem_map["com"], self.com.bus, 4)
self.add_memory_region("com", self.mem_map["com"], 4, type='io')
self.add_csr("com")
self.comb += self.com.oe.eq(
self.power.stats.fields.state
) # only drive to FPGA when it's powered up
# SPI port to wifi (controller) ------------------------------------------------------------------
self.submodules.wifi = ClockDomainsRenamer({'spi': 'sys'})(
SpiController(
platform.request("wifi"),
gpio_cs=True)) # control CS with GPIO per wf200 API spec
self.add_csr("wifi")
self.add_interrupt("wifi")
#### Platform config & build below ---------------------------------------------------------------
# Override default LiteX's yosys/build templates
assert hasattr(platform.toolchain, "yosys_template")
assert hasattr(platform.toolchain, "build_template")
platform.toolchain.yosys_template = [
"{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ice40 -json {build_name}.json -top {build_name}",
]
platform.toolchain.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
"icepack {build_name}.txt {build_name}.bin"
]
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.yosys_template[
2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
if use_dsp:
platform.toolchain.yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[
2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
if placer is not None:
platform.toolchain.build_template[1] += " --placer {}".format(
placer)
# Allow loops for RNG placement
platform.toolchain.build_template[1] += " --ignore-loops"
if sim:
class _WishboneBridge(Module):
def __init__(self, interface):
self.wishbone = interface
self.add_cpu(_WishboneBridge(self.platform.request("wishbone")))
self.add_wb_master(self.cpu.wishbone)
def __init__(self):
platform = tarjeta.Platform()
## add source verilog
platform.add_source("module/verilog/camara.v")
platform.add_source("module/verilog/Infrarrojo/modulo_ir.v")
platform.add_source("module/verilog/PWM/BloquePWM.v")
platform.add_source("module/verilog/PWM/PWM.v")
platform.add_source("module/verilog/PWM/MaquinaEstadosPWM.v")
platform.add_source("module/verilog/PWM/DivFreqPWM.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/bloqueultrasonido.v")
platform.add_source("module/verilog/Ultrasonido(NexysA7)/contador.v")
platform.add_source("module/verilog/Ultrasonido(NexysA7)/divisor.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrec.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrecd.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrecgen.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrecme.v")
platform.add_source("module/verilog/Ultrasonido(NexysA7)/genpulsos.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/maquinadeestados.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/meultrasonido.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/ultrasonido.v")
clk_freq = 100e6
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type="picorv32",
# cpu_type="vexriscv",
clk_freq=100e6,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(10)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(8)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*[platform.request("btn%c" % c) for c in ['c', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# RGB leds
SoCCore.add_csr(self, "ledRGB_1")
self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1))
SoCCore.add_csr(self, "ledRGB_2")
self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2))
# VGA
SoCCore.add_csr(self, "vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)])
self.submodules.vga_cntrl = vgacontroller.VGAcontroller(
platform.request("hsync"), platform.request("vsync"), vga_red,
vga_green, vga_blue)
#camara
"""
/* SoCCore.add_csr(self,"camara_cntrl")
SoCCore.add_interrupt(self,"camara_cntrl")
cam_data_in = Cat(*[platform.request("cam_data_in", i) for i in range(8)])
self.submodules.camara_cntrl = camara.Camara(platform.request("cam_xclk"),platform.request("cam_pclk"),cam_data_in)
"""
#serialA
from litex.soc.cores import uart
self.submodules.uart1_phy = uart.UARTPHY(
pads=platform.request("uart1"),
clk_freq=self.sys_clk_freq,
baudrate=9600)
self.submodules.uart1 = ResetInserter()(uart.UART(self.uart1_phy,
tx_fifo_depth=16,
rx_fifo_depth=16))
self.csr.add("uart1_phy", use_loc_if_exists=True)
self.csr.add("uart1", use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"):
self.irq.add("uart1", use_loc_if_exists=True)
else:
self.add_constant("UART_POLLING")
#Infrarrojo
SoCCore.add_csr(self, "infrarrojo_cntrl")
self.submodules.infrarrojo_cntrl = infrarrojo.Infrarrojo(
platform.request("ir_inout"))
#PWM
SoCCore.add_csr(self, "pwm_cntrl")
self.submodules.pwm_cntrl = pwm.PWM(platform.request("pwm_out"))
#Ultrasonido
SoCCore.add_csr(self, "ultrasonido")
self.submodules.ultrasonido = ultrasonido.Ultrasonido(
platform.request("us_trigger"), platform.request("us_echo"))
def __init__(self, platform, clk_freq,
# CPU parameters
cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
# MEM MAP parameters
shadow_base=0x80000000,
# ROM parameters
integrated_rom_size=0, integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=4096, integrated_sram_init=[],
# MAIN_RAM parameters
integrated_main_ram_size=0, integrated_main_ram_init=[],
# CSR parameters
csr_data_width=8, csr_alignment=32, csr_address_width=14,
# Identifier parameters
ident="", ident_version=False,
# UART parameters
with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False,
# Timer parameters
with_timer=True,
# Controller parameters
with_ctrl=True,
# Wishbone parameters
with_wishbone=True, wishbone_timeout_cycles=1e6):
self.platform = platform
self.clk_freq = clk_freq
# config dictionary (store all SoC's parameters to be exported to software)
self.config = dict()
# SoC's register/interrupt/memory mappings (default or user defined + dynamically allocateds)
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
# Regions / Constants lists
self._memory_regions = [] # (name, origin, length)
self._csr_regions = [] # (name, origin, busword, csr_list/Memory)
self._constants = [] # (name, value)
# Wishbone masters/slaves lists
self._wb_masters = []
self._wb_slaves = []
# CSR masters list
self._csr_masters = []
# Parameters managment ---------------------------------------------------------------------
# NOTE: RocketChip reserves the first 256Mbytes for internal use,
# so we must change default mem_map;
# Also, CSRs *must* be 64-bit aligned.
if cpu_type == "rocket":
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x11000000
self.soc_mem_map["csr"] = 0x12000000
csr_alignment = 64
# Mainline Linux OpenRISC arch code requires Linux kernel to be loaded
# at the physical address of 0x0. As we are running Linux from the
# MAIN_RAM region - move it to satisfy that requirement.
if cpu_type == "mor1kx" and cpu_variant == "linux":
self.soc_mem_map["main_ram"] = 0x00000000
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x50000000
self.soc_mem_map["csr"] = 0x60000000
if cpu_type == "None":
cpu_type = None
if not with_wishbone:
self.soc_mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
if integrated_rom_size:
cpu_reset_address = self.soc_mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.shadow_base = shadow_base
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 32, 64]
assert csr_alignment in [32, 64]
assert 2**(csr_address_width + 2) <= 0x1000000
self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------
# Add user's CSRs (needs to be done before the first dynamic allocation)
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
# Add SoCController
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
# Add CPU
self.config["CPU_TYPE"] = str(cpu_type).upper()
if cpu_type is not None:
if cpu_variant is not None:
self.config["CPU_VARIANT"] = str(cpu_variant.split('+')[0]).upper()
# CPU selection / instance
if cpu_type == "lm32":
self.add_cpu(cpu.lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "mor1kx" or cpu_type == "or1k":
if cpu_type == "or1k":
deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"")
self.add_cpu(cpu.mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "picorv32":
self.add_cpu(cpu.picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "vexriscv":
self.add_cpu(cpu.vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "minerva":
self.add_cpu(cpu.minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "rocket":
self.add_cpu(cpu.rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
# Add Instruction/Data buses as Wisbone masters
self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.cpu.dbus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", allow_user_defined=True)
# Add CPU reserved interrupts
for _name, _id in self.cpu.reserved_interrupts.items():
self.add_interrupt(_name, _id)
# Allow SoCController to reset the CPU
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
# Add user's interrupts (needs to be done after CPU reserved interrupts are allocated)
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
# Add integrated ROM
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size)
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
# Add UART
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
if uart_name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
elif uart_name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=platform.device)
else:
self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
# Add Timer
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
# Add Wishbone to CSR bridge
self.config["CSR_DATA_WIDTH"] = self.csr_data_width
self.config["CSR_ALIGNMENT"] = self.csr_alignment
if with_wishbone:
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(
address_width=self.csr_address_width,
data_width=self.csr_data_width))
self.add_csr_master(self.wishbone2csr.csr)
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000)
def __init__(self):
platform = tarjeta.Platform()
## add source verilog
platform.add_source("module/verilog/camara.v")
clk_freq = 100e6
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type="picorv32",
# cpu_type="vexriscv",
clk_freq=100e6,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(10)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(8)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*[platform.request("btn%c" % c) for c in ['c', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# RGB leds
SoCCore.add_csr(self, "ledRGB_1")
self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1))
SoCCore.add_csr(self, "ledRGB_2")
self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2))
# VGA
SoCCore.add_csr(self, "vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)])
self.submodules.vga_cntrl = vgacontroller.VGAcontroller(
platform.request("hsync"), platform.request("vsync"), vga_red,
vga_green, vga_blue)
#camara
SoCCore.add_csr(self, "camara_cntrl")
SoCCore.add_interrupt(self, "camara_cntrl")
cam_data_in = Cat(
*[platform.request("cam_data_in", i) for i in range(8)])
self.submodules.camara_cntrl = camara.Camara(
platform.request("cam_xclk"), platform.request("cam_pclk"),
cam_data_in)
#serialA
from litex.soc.cores import uart
self.submodules.uart1_phy = uart.UARTPHY(
pads=platform.request("uart1"),
clk_freq=self.sys_clk_freq,
baudrate=115200)
self.submodules.uart1 = ResetInserter()(uart.UART(self.uart1_phy,
tx_fifo_depth=16,
rx_fifo_depth=16))
self.csr.add("uart1_phy", use_loc_if_exists=True)
self.csr.add("uart1", use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"):
self.irq.add("uart1", use_loc_if_exists=True)
else:
self.add_constant("UART_POLLING")
