def _generate_csr_map(self, csr_json=None, csr_csv=None):
memory_regions = self.soc.get_memory_regions()
csr_regions = self.soc.get_csr_regions()
constants = self.soc.get_constants()
shadow_base = getattr(self.soc, "shadow_base", None)
if shadow_base:
constants.append(('shadow_base', shadow_base))
flash_boot_address = getattr(self.soc, "flash_boot_address", None)
if flash_boot_address:
constants.append(('flash_boot_address', flash_boot_address))
if csr_json is not None:
csr_dir = os.path.dirname(os.path.realpath(csr_json))
os.makedirs(csr_dir, exist_ok=True)
write_to_file(
csr_json,
cpu_interface.get_csr_json(csr_regions, constants,
memory_regions))
if csr_csv is not None:
csr_dir = os.path.dirname(os.path.realpath(csr_csv))
os.makedirs(csr_dir, exist_ok=True)
write_to_file(
csr_csv,
cpu_interface.get_csr_csv(csr_regions, constants,
memory_regions))
def _generate_csr_map(self, csr_json=None, csr_csv=None):
if csr_json is not None:
csr_dir = os.path.dirname(os.path.realpath(csr_json))
os.makedirs(csr_dir, exist_ok=True)
write_to_file(csr_json, cpu_interface.get_csr_json(self.soc.csr_regions, self.soc.constants, self.soc.mem_regions))
if csr_csv is not None:
csr_dir = os.path.dirname(os.path.realpath(csr_csv))
os.makedirs(csr_dir, exist_ok=True)
write_to_file(csr_csv, cpu_interface.get_csr_csv(self.soc.csr_regions, self.soc.constants, self.soc.mem_regions))
def _generate_csr_csv(self):
memory_regions = self.soc.get_memory_regions()
csr_regions = self.soc.get_csr_regions()
constants = self.soc.get_constants()
csr_dir = os.path.dirname(self.csr_csv)
os.makedirs(csr_dir, exist_ok=True)
write_to_file(
self.csr_csv,
cpu_interface.get_csr_csv(csr_regions, constants, memory_regions))
def _generate_csr_csv(self):
memory_regions = self.soc.get_memory_regions()
csr_regions = self.soc.get_csr_regions()
constants = self.soc.get_constants()
csr_dir = os.path.dirname(self.csr_csv)
os.makedirs(csr_dir, exist_ok=True)
write_to_file(
self.csr_csv,
cpu_interface.get_csr_csv(csr_regions, constants, memory_regions))
soc.clk_freq/1000000
)
)
# dependencies
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-csv"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = cpu_interface.get_csr_csv(csr_regions)
write_to_file(args.csr_csv, csr_csv)
if actions["build-bitstream"]:
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
vns = platform.build(soc, build_name=build_name, **build_kwargs)
if hasattr(soc, "do_exit") and vns is not None:
if hasattr(soc.do_exit, '__call__'):
soc.do_exit(vns)
if actions["load-bitstream"]:
prog = platform.create_programmer()
prog.load_bitstream("build/" + build_name + platform.bitstream_ext)
frequencies[revision]))
# dependencies
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-csv"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = cpu_interface.get_csr_csv(csr_regions, constants,
memory_regions)
write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]:
soc_fragment = soc.get_fragment()
platform.finalize(soc_fragment)
v_output = platform.get_verilog(
soc_fragment,
name="litesata",
special_overrides=xilinx_special_overrides)
v_output.write("build/litesata.v")
if actions["build-bitstream"]:
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
vns = platform.build(soc, build_name=build_name, **build_kwargs)
if hasattr(soc, "do_exit") and vns is not None:
# dependencies
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-csr-header"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-csv"] = True
actions["build-csr-header"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = cpu_interface.get_csr_csv(csr_regions)
write_to_file(args.csr_csv, csr_csv)
if actions["build-csr-header"]:
csr_header = cpu_interface.get_csr_header(csr_regions,
soc.get_constants(),
with_access_functions=False)
write_to_file(args.csr_header, csr_header)
if actions["build-bitstream"]:
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
vns = platform.build(soc, build_name=build_name, **build_kwargs)
if hasattr(soc, "do_exit") and vns is not None:
if hasattr(soc.do_exit, '__call__'):
soc.do_exit(vns)
soc.analyzer.depth))
# dependencies
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-csv"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = cpu_interface.get_csr_csv(csr_regions, csr_constants)
write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]:
soc_fragment = soc.get_fragment()
platform.finalize(soc_fragment)
v_output = platform.get_verilog(
soc_fragment,
name="litescope",
special_overrides=xilinx_special_overrides)
if not os.path.exists("build"):
os.makedirs("build")
v_output.write("build/litescope.v")
if actions["build-bitstream"]:
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
# dependencies
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-csr-header"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-csv"] = True
actions["build-csr-header"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = cpu_interface.get_csr_csv(csr_regions, soc.get_constants())
write_to_file(args.csr_csv, csr_csv)
if actions["build-csr-header"]:
csr_header = cpu_interface.get_csr_header(csr_regions,
soc.get_constants(),
with_access_functions=False)
write_to_file(args.csr_header, csr_header)
if actions["build-bitstream"]:
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
vns = platform.build(soc, build_name=build_name, **build_kwargs)
if hasattr(soc, "do_exit") and vns is not None:
if hasattr(soc.do_exit, '__call__'):
soc.do_exit(vns)
soc.analyzer.depth))
# dependencies
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-csv"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = cpu_interface.get_csr_csv(soc.csr_regions, soc.constants)
write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]:
soc_fragment = soc.get_fragment()
platform.finalize(soc_fragment)
v_output = platform.get_verilog(
soc_fragment,
name="litescope",
special_overrides=xilinx_special_overrides)
if not os.path.exists("build"):
os.makedirs("build")
v_output.write("build/litescope.v")
if actions["build-bitstream"]:
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
)
# dependencies
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-csv"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = cpu_interface.get_csr_csv(csr_regions, constants, memory_regions)
write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]:
soc_fragment = soc.get_fragment()
platform.finalize(soc_fragment)
so = {
NoRetiming: XilinxNoRetimingVivado,
MultiReg: XilinxMultiRegVivado,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
}
v_output = platform.get_verilog(soc_fragment, name="litesata", special_overrides=so)
v_output.write("build/litesata.v")
if actions["build-bitstream"]:
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
]
# define platform/core
platform = CorePlatform()
core = Core(platform)
# generate verilog
v_output = platform.get_verilog(core, name="litescope")
v_output.write("litescope.v")
# generate csr.csv
memory_regions = core.get_memory_regions()
csr_regions = core.get_csr_regions()
constants = core.get_constants()
write_to_file("csr.csv", cpu_interface.get_csr_csv(csr_regions, constants, memory_regions))
# generate analyzer.csv
core.analyzer.export_csv(v_output.ns, "analyzer.csv")
"""
assign videooverlaysoc_litescope_bus = {
videooverlaysoc_videooverlaysoc_videooverlaysoc_ibus_sel[3:0],
1'b0,
videooverlaysoc_videooverlaysoc_videooverlaysoc_ibus_err,
videooverlaysoc_videooverlaysoc_videooverlaysoc_ibus_ack,
videooverlaysoc_videooverlaysoc_videooverlaysoc_ibus_stb,
videooverlaysoc_hdmi_in1_dma_current_address[23:0],
videooverlaysoc_videooverlaysoc_videooverlaysoc_interrupt[31:0],
videooverlaysoc_videooverlaysoc_videooverlaysoc_ibus_dat_r[31:0],
videooverlaysoc_videooverlaysoc_videooverlaysoc_i_adr_o[31:0] };
