def generate_software_headers(self):
csr_header = get_csr_header(self.csr_regions, self.constants, with_access_functions=False)
tools.write_to_file(os.path.join("build", "csr.h"), csr_header)
soc_header = get_soc_header(self.constants, with_access_functions=False)
tools.write_to_file(os.path.join("build", "soc.h"), soc_header)
mem_header = get_mem_header(self.mem_regions)
tools.write_to_file(os.path.join("build", "mem.h"), mem_header)
def main():
parser = argparse.ArgumentParser(description="Opsis LiteX SoC",
conflict_handler='resolve')
get_args(parser)
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
platform = get_platform(args)
soc = get_soc(args, platform)
builddir = get_builddir(args)
testdir = get_testdir(args)
buildargs = builder_argdict(args)
if not buildargs.get('output_dir', None):
buildargs['output_dir'] = builddir
if hasattr(soc, 'cpu_type'):
if not buildargs.get('csr_csv', None):
buildargs['csr_csv'] = os.path.join(testdir, "csr.csv")
if not buildargs.get('csr_json', None):
buildargs['csr_json'] = os.path.join(testdir, "csr.json")
builder = Builder(soc, **buildargs)
if not args.no_compile_firmware or args.override_firmware:
builder.add_software_package("uip",
"{}/firmware/uip".format(os.getcwd()))
# FIXME: All platforms which current run their user programs from
# SPI flash lack the block RAM resources to run the default
# firmware. Check whether to use the stub or default firmware
# should be refined (perhaps soc attribute?).
if "main_ram" in soc.mem_regions:
builder.add_software_package("firmware",
"{}/firmware".format(os.getcwd()))
else:
builder.add_software_package(
"stub", "{}/firmware/stub".format(os.getcwd()))
vns = builder.build(**dict(args.build_option))
else:
vns = platform.build(soc, build_dir=os.path.join(builddir, "gateware"))
if hasattr(soc, 'pcie_phy'):
from litex.soc.integration.export import get_csr_header, get_soc_header
csr_header = get_csr_header(soc.csr_regions,
soc.constants,
with_access_functions=False)
soc_header = get_soc_header(soc.constants, with_access_functions=False)
kerneldir = os.path.join(builddir, "software", "pcie", "kernel")
os.makedirs(kerneldir, exist_ok=True)
write_to_file(os.path.join(kerneldir, "csr.h"), csr_header)
write_to_file(os.path.join(kerneldir, "soc.h"), soc_header)
if hasattr(soc, 'do_exit'):
soc.do_exit(vns, filename="{}/analyzer.csv".format(testdir))
def _generate_includes(self):
os.makedirs(self.include_dir, exist_ok=True)
os.makedirs(self.generated_dir, exist_ok=True)
if self.soc.cpu_type not in [None, "zynq7000"]:
variables_contents = []
def define(k, v):
variables_contents.append("{}={}\n".format(k, _makefile_escape(v)))
for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software):
define(k, v)
define(
"COMPILER_RT_DIRECTORY",
get_data_mod("software", "compiler_rt").data_location)
define("SOC_DIRECTORY", soc_directory)
variables_contents.append("export BUILDINC_DIRECTORY\n")
define("BUILDINC_DIRECTORY", self.include_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
for bios_option in self.bios_options:
assert bios_option in ["TERM_NO_HIST", "TERM_MINI", "TERM_NO_COMPLETE"]
define(bios_option, "1")
write_to_file(
os.path.join(self.generated_dir, "variables.mak"),
"".join(variables_contents))
write_to_file(
os.path.join(self.generated_dir, "output_format.ld"),
export.get_linker_output_format(self.soc.cpu))
write_to_file(
os.path.join(self.generated_dir, "regions.ld"),
export.get_linker_regions(self.soc.mem_regions))
write_to_file(
os.path.join(self.generated_dir, "mem.h"),
export.get_mem_header(self.soc.mem_regions))
write_to_file(
os.path.join(self.generated_dir, "soc.h"),
export.get_soc_header(self.soc.constants))
write_to_file(
os.path.join(self.generated_dir, "csr.h"),
export.get_csr_header(
regions = self.soc.csr_regions,
constants = self.soc.constants,
csr_base = self.soc.mem_regions['csr'].origin
)
)
write_to_file(
os.path.join(self.generated_dir, "git.h"),
export.get_git_header()
)
if hasattr(self.soc, "sdram"):
from litedram.init import get_sdram_phy_c_header
write_to_file(os.path.join(self.generated_dir, "sdram_phy.h"),
get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing))
def _generate_includes(self, with_bios=True):
# Generate Include/Generated directories.
_create_dir(self.include_dir)
_create_dir(self.generated_dir)
# Generate BIOS files when the SoC uses it.
if with_bios:
# Generate Variables to variables.mak.
variables_contents = self._get_variables_contents()
write_to_file(os.path.join(self.generated_dir, "variables.mak"), variables_contents)
# Generate Output Format to output_format.ld.
output_format_contents = export.get_linker_output_format(self.soc.cpu)
write_to_file(os.path.join(self.generated_dir, "output_format.ld"), output_format_contents)
# Generate Memory Regions to regions.ld.
regions_contents = export.get_linker_regions(self.soc.mem_regions)
write_to_file(os.path.join(self.generated_dir, "regions.ld"), regions_contents)
# Collect / Generate I2C config and init table.
from litex.soc.cores.bitbang import collect_i2c_info
i2c_devs, i2c_init = collect_i2c_info(self.soc)
if i2c_devs:
i2c_info = export.get_i2c_header((i2c_devs, i2c_init))
write_to_file(os.path.join(self.generated_dir, "i2c.h"), i2c_info)
# Generate Memory Regions to mem.h.
mem_contents = export.get_mem_header(self.soc.mem_regions)
write_to_file(os.path.join(self.generated_dir, "mem.h"), mem_contents)
# Generate Memory Regions to memory.x if specified.
if self.memory_x is not None:
memory_x_contents = export.get_memory_x(self.soc)
write_to_file(os.path.realpath(self.memory_x), memory_x_contents)
# Generate SoC Config/Constants to soc.h.
soc_contents = export.get_soc_header(self.soc.constants)
write_to_file(os.path.join(self.generated_dir, "soc.h"), soc_contents)
# Generate CSR registers definitions/access functions to csr.h.
csr_contents = export.get_csr_header(
regions = self.soc.csr_regions,
constants = self.soc.constants,
csr_base = self.soc.mem_regions['csr'].origin)
write_to_file(os.path.join(self.generated_dir, "csr.h"), csr_contents)
# Generate Git SHA1 of tools to git.h
git_contents = export.get_git_header()
write_to_file(os.path.join(self.generated_dir, "git.h"), git_contents)
# Generate LiteDRAM C header to sdram_phy.h when the SoC use it
if hasattr(self.soc, "sdram"):
from litedram.init import get_sdram_phy_c_header
sdram_contents = get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing)
write_to_file(os.path.join(self.generated_dir, "sdram_phy.h"), sdram_contents)
def _generate_includes(self):
os.makedirs(self.include_dir, exist_ok=True)
os.makedirs(self.generated_dir, exist_ok=True)
if self.soc.cpu_type is not None:
variables_contents = []
def define(k, v):
variables_contents.append("{}={}\n".format(
k, _makefile_escape(v)))
for k, v in export.get_cpu_mak(self.soc.cpu,
self.compile_software):
define(k, v)
# Distinguish between LiteX and MiSoC.
define("LITEX", "1")
# Distinguish between applications running from main RAM and
# flash for user-provided software packages.
exec_profiles = {"COPY_TO_MAIN_RAM": "0", "EXECUTE_IN_PLACE": "0"}
if "main_ram" in self.soc.mem_regions.keys():
exec_profiles["COPY_TO_MAIN_RAM"] = "1"
else:
exec_profiles["EXECUTE_IN_PLACE"] = "1"
for k, v in exec_profiles.items():
define(k, v)
define("COMPILER_RT_DIRECTORY",
get_data_mod("software", "compiler_rt").data_location)
define("SOC_DIRECTORY", soc_directory)
variables_contents.append("export BUILDINC_DIRECTORY\n")
define("BUILDINC_DIRECTORY", self.include_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
write_to_file(os.path.join(self.generated_dir, "variables.mak"),
"".join(variables_contents))
write_to_file(os.path.join(self.generated_dir, "output_format.ld"),
export.get_linker_output_format(self.soc.cpu))
write_to_file(os.path.join(self.generated_dir, "regions.ld"),
export.get_linker_regions(self.soc.mem_regions))
write_to_file(os.path.join(self.generated_dir, "mem.h"),
export.get_mem_header(self.soc.mem_regions))
write_to_file(os.path.join(self.generated_dir, "soc.h"),
export.get_soc_header(self.soc.constants))
write_to_file(
os.path.join(self.generated_dir, "csr.h"),
export.get_csr_header(self.soc.csr_regions, self.soc.constants))
write_to_file(os.path.join(self.generated_dir, "git.h"),
export.get_git_header())
if hasattr(self.soc, "sdram"):
from litedram.init import get_sdram_phy_c_header
write_to_file(
os.path.join(self.generated_dir, "sdram_phy.h"),
get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing))
def write_usb_csr(self, directory):
csrs = self.usb0.get_csr()
from litex.soc.integration import export
from litex.build.tools import write_to_file
from litex.soc.integration.soc_core import SoCCSRRegion
os.makedirs(directory, exist_ok=True)
write_to_file(
os.path.join(directory, "csr_usb.h"),
export.get_csr_header({"usb": SoCCSRRegion(0x90000000, 32, csrs)},
self.constants))
def _generate_includes(self):
# Generate Include/Generated directories.
_create_dir(self.include_dir)
_create_dir(self.generated_dir)
# Generate BIOS files when the SoC uses it.
with_bios = self.soc.cpu_type not in [None, "zynq7000"]
if with_bios:
# Generate Variables to variables.mak.
variables_contents = []
def define(k, v):
variables_contents.append("{}={}".format(
k, _makefile_escape(v)))
# Define the CPU variables.
for k, v in export.get_cpu_mak(self.soc.cpu,
self.compile_software):
define(k, v)
# Define the SoC/Compiler-RT/Software/Include directories.
define("SOC_DIRECTORY", soc_directory)
compiler_rt_directory = get_data_mod("software",
"compiler_rt").data_location
define("COMPILER_RT_DIRECTORY", compiler_rt_directory)
variables_contents.append("export BUILDINC_DIRECTORY")
define("BUILDINC_DIRECTORY", self.include_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
# Define the BIOS Options.
for bios_option in self.bios_options:
assert bios_option in [
"TERM_NO_HIST", "TERM_MINI", "TERM_NO_COMPLETE"
]
define(bios_option, "1")
# Write to variables.mak.
write_to_file(os.path.join(self.generated_dir, "variables.mak"),
"\n".join(variables_contents))
# Generate Output Format to output_format.ld.
output_format_contents = export.get_linker_output_format(
self.soc.cpu)
write_to_file(os.path.join(self.generated_dir, "output_format.ld"),
output_format_contents)
# Generate Memory Regions to regions.ld.
regions_contents = export.get_linker_regions(self.soc.mem_regions)
write_to_file(os.path.join(self.generated_dir, "regions.ld"),
regions_contents)
# Generate Memory Regions to mem.h.
mem_contents = export.get_mem_header(self.soc.mem_regions)
write_to_file(os.path.join(self.generated_dir, "mem.h"), mem_contents)
# Generate Memory Regions to memory.x if specified.
if self.memory_x is not None:
memory_x_contents = export.get_memory_x(self.soc)
write_to_file(os.path.realpath(self.memory_x), memory_x_contents)
# Generate SoC Config/Constants to soc.h.
soc_contents = export.get_soc_header(self.soc.constants)
write_to_file(os.path.join(self.generated_dir, "soc.h"), soc_contents)
# Generate CSR registers definitions/access functions to csr.h.
csr_contents = export.get_csr_header(
regions=self.soc.csr_regions,
constants=self.soc.constants,
csr_base=self.soc.mem_regions['csr'].origin)
write_to_file(os.path.join(self.generated_dir, "csr.h"), csr_contents)
# Generate Git SHA1 of tools to git.h
git_contents = export.get_git_header()
write_to_file(os.path.join(self.generated_dir, "git.h"), git_contents)
# Generate LiteDRAM C header to sdram_phy.h when the SoC use it.
if hasattr(self.soc, "sdram"):
from litedram.init import get_sdram_phy_c_header
sdram_contents = get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing)
write_to_file(os.path.join(self.generated_dir, "sdram_phy.h"),
sdram_contents)
def generate_software_header(self):
csr_header = get_csr_header(self.csr_regions,
self.constants,
with_access_functions=False,
with_shadow_base=False)
tools.write_to_file(os.path.join("software", "pcie", "kernel", "csr.h"), csr_header)
def generate_software_header(self, filename):
csr_header = get_csr_header(self.csr_regions,
self.constants,
with_access_functions=False)
tools.write_to_file(filename, csr_header)
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-csr-header"] = True
actions["build-soc-header"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-header"] = True
actions["build-soc-header"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-header"]:
csr_header = export.get_csr_header(soc.csr_regions, soc.constants, with_access_functions=False)
write_to_file(args.csr_header, csr_header)
if actions["build-soc-header"]:
soc_header = export.get_soc_header(soc.constants, with_access_functions=False)
write_to_file(args.soc_header, soc_header)
if actions["build-bitstream"]:
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
vns = platform.build(soc, build_name=build_name, **build_kwargs)
if hasattr(soc, "do_exit") and vns is not None:
if hasattr(soc.do_exit, '__call__'):
soc.do_exit(vns)
if actions["load-bitstream"]:
prog = platform.create_programmer()
