def _initialize_rom_software(self):
# Get BIOS data from compiled BIOS binary.
bios_file = os.path.join(self.software_dir, "bios", "bios.bin")
bios_data = soc_core.get_mem_data(bios_file, self.soc.cpu.endianness)
# Initialize SoC with with BIOS data.
self.soc.initialize_rom(bios_data)
def main():
parser = argparse.ArgumentParser(
description="Build test file for dummy or eptri module")
builder_args(parser)
soc_core_args(parser)
parser.add_argument('--dir',
metavar='DIRECTORY',
default='build',
help='Output directory (defauilt: %(default)s)')
parser.add_argument('--csr',
metavar='CSR',
default='csr.csv',
help='csr file (default: %(default)s)')
parser.add_argument("--rom-init", default=None, help="rom_init file")
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
if args.rom_init is not None:
soc_kwargs["integrated_rom_init"] = \
get_mem_data(args.rom_init, endianness='little')
output_dir = args.dir
platform = Platform()
soc = BaseSoC(platform, **soc_kwargs)
builder = Builder(soc,
output_dir=output_dir,
csr_csv=args.csr,
compile_software=False)
vns = builder.build(run=False)
soc.do_exit(vns)
print("""Simulation build complete. Output files:
{}/gateware/dut.v Source Verilog file. Run this under Cocotb.
""".format(output_dir))
def main():
parser = argparse.ArgumentParser(
formatter_class=argparse.RawTextHelpFormatter)
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load",
action="store_true",
help="Load bitstream (to SRAM)")
VexRiscvSMP.args_fill(parser)
args = parser.parse_args()
# build bootrom
subprocess.check_call("make", cwd="bootrom")
# CPU parameters ---------------------------------------------------------------------------
# Do memory accesses through Wishbone and L2 cache when L2 size is configured.
args.with_wishbone_memory = True
VexRiscvSMP.args_read(args)
# SoC creation -----------------------------------------------------------------------------
soc_kwargs = {
"integrated_sram_size": 0x0,
"integrated_rom_size": 0x400,
"l2_size": 0x4000, # Use Wishbone and L2 for memory accesses.
"with_uart": False,
}
rom_data = get_mem_data("bootrom/rom.bin",
endianness="little",
mem_size=soc_kwargs["integrated_rom_size"])
soc_kwargs["integrated_rom_init"] = rom_data
soc = De0SoC(**soc_kwargs)
board_name = "de0nano"
# Build ------------------------------------------------------------------------------------
build_dir = os.path.join("build", board_name)
builder = Builder(soc,
csr_json=os.path.join(build_dir, "csr.json"),
csr_csv=os.path.join(build_dir, "csr.csv"),
compile_software=False)
builder.build(run=args.build)
# DTS --------------------------------------------------------------------------------------
generate_dts(board_name)
compile_dts(board_name)
# Load FPGA bitstream ----------------------------------------------------------------------
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
def main():
parser = argparse.ArgumentParser(description=__doc__)
builder_args(parser)
MySoc.basesoc_args(parser)
parser.add_argument("--trace", action="store_true",
help="enable VCD tracing")
parser.add_argument("--rom-init", default=None,
help="rom_init file")
parser.set_defaults(
integrated_rom_size=0x8000,
integrated_main_ram_size=0x8000,
# integrated_sram_size=0, # Litex will complain if 0!
cpu_type="vexriscv",
platform="cmod_a7_sim",
clk_freq=int(1e6),
with_uart=False # We will add our own mock uart
)
args = parser.parse_args()
soc_kwargs = vars(args)
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
soc = MySoc(crg=CRG, **soc_kwargs)
# Push in a fake uart
soc.submodules.uart_phy = uart.RS232PHYModel(soc.platform.request("serial"))
soc.submodules.uart = uart.UART(soc.uart_phy)
sim_config = SimConfig(default_clk="sys_clk")
# sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
sim_config.add_module("serial2console", "serial")
# sim_config.add_module("serial2tcp", "serial", args={"port": 55555})
# now you can do these 2 things to get a terminal
# telnet localhost 55555
# litex_term socket://localhost:55555
# soc.add_constant("TFTP_SERVER_PORT", int(tftp_port))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=False, sim_config=sim_config, trace=args.trace)
def _initialize_rom(self):
bios_file = os.path.join(self.output_dir, "software", "bios",
"bios.bin")
bios_data = soc_core.get_mem_data(bios_file, self.soc.cpu.endianness)
self.soc.initialize_rom(bios_data)
"""\
Convert .bin to verilog .mem file and print to stdout
usage: bin2init.py boot.bin little
"""
from litex.soc.integration.soc_core import get_mem_data
from sys import argv
if len(argv) != 3:
print(__doc__)
else:
dats = get_mem_data("./boot.bin", "little")
for dat in dats:
print("{:08x}".format(dat))
def _initialize_rom(self):
bios_file = os.path.join(self.output_dir, "software", "bios","bios.bin")
bios_data = soc_core.get_mem_data(bios_file, self.soc.cpu.endianness)
self.soc.initialize_rom(bios_data)
