def main():
parser = argparse.ArgumentParser(description="LiteX SoC on MarbleMini")
builder_args(parser)
soc_sdram_args(parser)
# soc_core_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--ethernet-phy",
default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
parser.add_argument("-p",
"--program-only",
action="store_true",
help="select Ethernet PHY (rgmii or 1000basex)")
args = parser.parse_args()
if args.with_ethernet:
soc = LTCSocDev(phy=args.ethernet_phy, **soc_sdram_argdict(args))
# soc = EthernetSoC(phy=args.ethernet_phy, **soc_sdram_argdict(args))
# soc = EthernetSoC(phy=args.ethernet_phy, **soc_core_argdict(args))
else:
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
if not args.program_only:
vns = builder.build()
if False:
soc.analyzer.do_exit(vns)
prog = soc.platform.create_programmer()
import os
prog.load_bitstream(os.path.join(builder.gateware_dir, "marblemini.bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
builder_args(parser)
soc_sdram_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
cls = MinSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args))
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC on the Arrow/Terasic SoCKit")
parser.add_argument(
"--single-rate-sdram",
action="store_true",
help="clock SDRAM with 1x the sytem clock (instead of 2x)")
parser.add_argument(
"--mister-sdram-xs-v22",
action="store_true",
help=
"Use optional MiSTer SDRAM module XS v2.2 on J2 on GPIO daughter card")
parser.add_argument(
"--mister-sdram-xs-v24",
action="store_true",
help=
"Use optional MiSTer SDRAM module XS v2.4 on J2 on GPIO daughter card")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--revision",
default="revd",
help="Board revision: revb (default), revc or revd")
parser.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency (default: 50MHz)")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
revision=args.revision,
sdram_rate="1:1" if args.single_rate_sdram else "1:2",
mister_sdram="xs_v22" if args.mister_sdram_xs_v22 else
"xs_v24" if args.mister_sdram_xs_v24 else None,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on SoCKit")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--revision",
default="revd",
help="Board revision: revb (default), revc or revd")
parser.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency (default: 50MHz)")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
revision=args.revision,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
builder_args(parser.add_argument_group(title="Builder"))
soc_sdram_args(parser.add_argument_group(title="SoC SDRAM"))
group = parser.add_argument_group(title="LPDDR4 simulation")
group.add_argument("--sdram-verbosity",
default=0,
help="Set SDRAM checker verbosity")
group.add_argument("--trace", action="store_true", help="Enable Tracing")
group.add_argument("--trace-fst",
action="store_true",
help="Enable FST tracing (default=VCD)")
group.add_argument("--trace-start",
default=0,
help="Cycle to start tracing")
group.add_argument("--trace-end", default=-1, help="Cycle to end tracing")
group.add_argument("--trace-reset",
default=0,
help="Initial traceing state")
group.add_argument("--sys-clk-freq",
default="50e6",
help="Core clock frequency")
group.add_argument("--auto-precharge",
action="store_true",
help="Use DRAM auto precharge")
group.add_argument("--no-refresh",
action="store_true",
help="Disable DRAM refresher")
group.add_argument("--log-level",
default="all=INFO",
help="Set simulation logging level")
group.add_argument("--disable-delay",
action="store_true",
help="Disable CPU delays")
group.add_argument("--gtkw-savefile",
action="store_true",
help="Generate GTKWave savefile")
group.add_argument("--no-masked-write",
action="store_true",
help="Use LPDDR4 WRITE instead of MASKED-WRITE")
group.add_argument("--no-run",
action="store_true",
help="Don't run the simulation, just generate files")
group.add_argument("--double-rate-phy",
action="store_true",
help="Use sim PHY with 2-stage serialization")
group.add_argument("--finish-after-memtest",
action="store_true",
help="Stop simulation after DRAM memory test")
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig()
sys_clk_freq = int(float(args.sys_clk_freq))
clocks = get_clocks(sys_clk_freq)
clocks.add_io(_io)
clocks.add_clockers(sim_config)
# Configuration --------------------------------------------------------------------------------
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
args.with_sdram = True
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(clocks=clocks,
auto_precharge=args.auto_precharge,
with_refresh=not args.no_refresh,
trace_reset=int(args.trace_reset),
log_level=args.log_level,
disable_delay=args.disable_delay,
masked_write=not args.no_masked_write,
double_rate_phy=args.double_rate_phy,
finish_after_memtest=args.finish_after_memtest,
**soc_kwargs)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
build_kwargs = dict(sim_config=sim_config,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
vns = builder.build(run=False, **build_kwargs)
if args.gtkw_savefile:
generate_gtkw_savefile(builder, vns, trace_fst=args.trace_fst)
if not args.no_run:
builder.build(build=False, **build_kwargs)