def __init__(self, platform, variant): self.platform = platform self.variant = "standard" self.human_name = self.human_name self.reset = Signal() self.interrupt = Signal(32) self.ibus = ibus = axi.AXILiteInterface(address_width=32, data_width=64) self.dbus = dbus = axi.AXILiteInterface(address_width=32, data_width=64) self.periph_buses = [ ibus, dbus ] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [ ] # Memory buses (Connected directly to LiteDRAM). # # # # CPU Instance. self.cpu_params = dict( # Clk/Rst. i_clk=ClockSignal("sys"), i_reset=ResetSignal("sys") | self.reset, # Interrupt. i_peripheral_interrupt=self. interrupt, # FIXME: Check what is expected. => interrupt(0) is dummy and should not be used (PLIC stuff), need to reserve interrupt(0) # Peripheral Instruction Bus (AXI Lite Slave). o_peripheral_ibus_arvalid=ibus.ar.valid, i_peripheral_ibus_arready=ibus.ar.ready, o_peripheral_ibus_araddr=ibus.ar.addr, o_peripheral_ibus_arprot=Open(), i_peripheral_ibus_rvalid=ibus.r.valid, o_peripheral_ibus_rready=ibus.r.ready, i_peripheral_ibus_rdata=ibus.r.data, i_peripheral_ibus_rresp=ibus.r.resp, # Peripheral Memory Bus (AXI Lite Slave). o_peripheral_dbus_awvalid=dbus.aw.valid, i_peripheral_dbus_awready=dbus.aw.ready, o_peripheral_dbus_awaddr=dbus.aw.addr, o_peripheral_dbus_awprot=Open(), o_peripheral_dbus_wvalid=dbus.w.valid, i_peripheral_dbus_wready=dbus.w.ready, o_peripheral_dbus_wdata=dbus.w.data, o_peripheral_dbus_wstrb=dbus.w.strb, i_peripheral_dbus_bvalid=dbus.b.valid, o_peripheral_dbus_bready=dbus.b.ready, i_peripheral_dbus_bresp=dbus.b.resp, o_peripheral_dbus_arvalid=dbus.ar.valid, i_peripheral_dbus_arready=dbus.ar.ready, o_peripheral_dbus_araddr=dbus.ar.addr, o_peripheral_dbus_arprot=Open(), i_peripheral_dbus_rvalid=dbus.r.valid, o_peripheral_dbus_rready=dbus.r.ready, i_peripheral_dbus_rdata=dbus.r.data, i_peripheral_dbus_rresp=dbus.r.resp, )
def __init__(self, name="litex_soc", sys_clk_freq=int(50e6), **kwargs): # Platform --------------------------------------------------------------------------------- platform = Platform(device="", io=get_common_ios()) platform.name = name platform.add_extension(get_uart_ios()) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG( clk=platform.request("clk"), rst=platform.request("rst"), ) # SoC -------------------------------------------------------------------------------------- if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "uart" SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident=f"LiteX standalone SoC - {name}", **kwargs) # MMAP Slave Interface --------------------------------------------------------------------- s_bus = { "wishbone": wishbone.Interface(), "axi-lite": axi.AXILiteInterface(), }[kwargs["bus_standard"]] self.bus.add_master(name="mmap_s", master=s_bus) platform.add_extension(s_bus.get_ios("mmap_s")) wb_pads = platform.request("mmap_s") self.comb += s_bus.connect_to_pads(wb_pads, mode="slave") # MMAP Master Interface -------------------------------------------------------------------- # FIXME: Allow Region configuration. m_bus = { "wishbone": wishbone.Interface(), "axi-lite": axi.AXILiteInterface(), }[kwargs["bus_standard"]] wb_region = SoCRegion(origin=0xa000_0000, size=0x1000_0000, cached=False) # FIXME. self.bus.add_slave(name="mmap_m", slave=m_bus, region=wb_region) platform.add_extension(m_bus.get_ios("mmap_m")) wb_pads = platform.request("mmap_m") self.comb += m_bus.connect_to_pads(wb_pads, mode="master") # Debug ------------------------------------------------------------------------------------ platform.add_extension(get_debug_ios()) debug_pads = platform.request("debug") self.comb += [ # Export Signal(s) for debug. debug_pads[0].eq(0), # 0. debug_pads[1].eq(1), # 1. # Etc... ]
def __init__(self, **kwargs): super().__init__(**kwargs) # ZynqUS+ PS ------------------------------------------------------------------------------- if not self.args.sim: # Add Zynq US+ PS wrapper self.submodules.ps = ZynqUSPS() # Configure PS->PL AXI # AXI(128) -> AXILite(128) -> AXILite(32) -> WishBone(32) -> SoC Interconnect axi_ps = self.ps.add_axi_gp_fpd_master() axi_lite_ps = axi.AXILiteInterface( data_width=axi_ps.data_width, address_width=axi_ps.address_width) self.submodules += axi.AXI2AXILite(axi_ps, axi_lite_ps) axi_lite_ps_32 = axi.AXILiteInterface(data_width=32, address_width=40) self.submodules += axi.AXILiteConverter(axi_lite_ps, axi_lite_ps_32) # Use M_AXI_HPM0_FPD base address thaht will fit our whole address space (0x0004_0000_0000) base_address = None for base, size in self.ps.PS_MEMORY_MAP['gp_fpd_master'][0]: if size >= 2**30 - 1: base_address = base break assert base_address is not None def chunks(lst, n): for i in range(0, len(lst), n): yield lst[i:i + n] addr_str = '_'.join(chunks('{:012x}'.format(base_address), 4)) self.logger.info( "Connecting PS AXI master from PS address {}.".format( colorer('0x' + addr_str))) wb_ps = wishbone.Interface( adr_width=40 - 2) # AXILite2Wishbone requires the same address widths self.submodules += axi.AXILite2Wishbone(axi_lite_ps_32, wb_ps, base_address=base_address) # silently ignores address bits above 30 self.bus.add_master(name='ps_axi', master=wb_ps)
def __init__(self, **kwargs): min_rom = 0x9000 if kwargs["integrated_rom_size"] < min_rom: kwargs["integrated_rom_size"] = min_rom super().__init__(**kwargs) if self.args.sim: return # SPD EEPROM I2C --------------------------------------------------------------------------- self.submodules.i2c = I2CMaster(self.platform.request("i2c")) self.add_csr("i2c") # ZynqUS+ PS ------------------------------------------------------------------------------- self.submodules.ps = ZynqUSPS() # Configure PS->PL AXI # AXI(32) -> AXILite(32) -> WishBone(32) -> SoC Interconnect axi_ps = self.ps.add_axi_gp_fpd_master(data_width=32) axi_lite_ps = axi.AXILiteInterface(data_width=32, address_width=40) self.submodules += axi.AXI2AXILite(axi_ps, axi_lite_ps) # Use M_AXI_HPM0_FPD base address thaht will fit our whole address space (0x0004_0000_0000) base_address = None for base, size in self.ps.PS_MEMORY_MAP['gp_fpd_master'][0]: if size >= 2**30 - 1: base_address = base break assert base_address is not None def chunks(lst, n): for i in range(0, len(lst), n): yield lst[i:i + n] addr_str = '_'.join(chunks('{:012x}'.format(base_address), 4)) self.logger.info("Connecting PS AXI master from PS address {}.".format( colorer('0x' + addr_str))) wb_ps = wishbone.Interface( adr_width=40 - 2) # AXILite2Wishbone requires the same address widths self.submodules += axi.AXILite2Wishbone(axi_lite_ps, wb_ps, base_address=base_address) # silently ignores address bits above 30 self.bus.add_master(name='ps_axi', master=wb_ps)
def add_soc_components(self, soc, soc_region_cls): # Set UART/Timer0 CSRs/IRQs to the ones used by OpenSBI. soc.csr.add("uart", n=2) soc.csr.add("timer0", n=3) soc.irq.add("uart", n=0) soc.irq.add("timer0", n=1) # Add OpenSBI region. soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f00000, 0x80000, type="cached+linker") # Define ISA. soc.add_constant("CPU_ISA", NaxRiscv.get_arch()) # Add PLIC Bus (Wishbone Slave). self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32) self.cpu_params.update( i_peripheral_plic_awvalid = plicbus.aw.valid, o_peripheral_plic_awready = plicbus.aw.ready, i_peripheral_plic_awaddr = plicbus.aw.addr, i_peripheral_plic_awprot = Constant(2), i_peripheral_plic_wvalid = plicbus.w.valid, o_peripheral_plic_wready = plicbus.w.ready, i_peripheral_plic_wdata = plicbus.w.data, i_peripheral_plic_wstrb = plicbus.w.strb, o_peripheral_plic_bvalid = plicbus.b.valid, i_peripheral_plic_bready = plicbus.b.ready, o_peripheral_plic_bresp = plicbus.b.resp, i_peripheral_plic_arvalid = plicbus.ar.valid, o_peripheral_plic_arready = plicbus.ar.ready, i_peripheral_plic_araddr = plicbus.ar.addr, i_peripheral_plic_arprot = Constant(2), o_peripheral_plic_rvalid = plicbus.r.valid, i_peripheral_plic_rready = plicbus.r.ready, o_peripheral_plic_rdata = plicbus.r.data, o_peripheral_plic_rresp = plicbus.r.resp, ) soc.bus.add_slave("plic", self.plicbus, region=soc_region_cls(origin=soc.mem_map.get("plic"), size=0x400000, cached=False)) # Add CLINT Bus (Wishbone Slave). self.clintbus = clintbus = axi.AXILiteInterface(address_width=32, data_width=32) self.cpu_params.update( i_peripheral_clint_awvalid = clintbus.aw.valid, o_peripheral_clint_awready = clintbus.aw.ready, i_peripheral_clint_awaddr = clintbus.aw.addr, i_peripheral_clint_awprot = Constant(2), i_peripheral_clint_wvalid = clintbus.w.valid, o_peripheral_clint_wready = clintbus.w.ready, i_peripheral_clint_wdata = clintbus.w.data, i_peripheral_clint_wstrb = clintbus.w.strb, o_peripheral_clint_bvalid = clintbus.b.valid, i_peripheral_clint_bready = clintbus.b.ready, o_peripheral_clint_bresp = clintbus.b.resp, i_peripheral_clint_arvalid = clintbus.ar.valid, o_peripheral_clint_arready = clintbus.ar.ready, i_peripheral_clint_araddr = clintbus.ar.addr, i_peripheral_clint_arprot = Constant(2), o_peripheral_clint_rvalid = clintbus.r.valid, i_peripheral_clint_rready = clintbus.r.ready, o_peripheral_clint_rdata = clintbus.r.data, o_peripheral_clint_rresp = clintbus.r.resp, ) soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x10000, cached=False))
def __init__(self, sys_clk_freq=int(100e6), with_pwm=False, with_gpio=False, gpio_width=32, with_spi_master=False, spi_master_data_width=8, spi_master_clk_freq=8e6, **kwargs): platform = Platform(_io) # UART if kwargs["with_uart"]: platform.add_extension([( "serial", 0, Subsignal("tx", Pins(1)), Subsignal("rx", Pins(1)), )]) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst")) # SoCMini ---------------------------------------------------------------------------------- print(kwargs) SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # SPI Master if with_spi_master: platform.add_extension([( "spi_master", 0, Subsignal("clk", Pins(1)), Subsignal("cs_n", Pins(1)), Subsignal("mosi", Pins(1)), Subsignal("miso", Pins(1)), )]) self.submodules.spi_master = SPIMaster( pads=platform.request("spi_master"), data_width=spi_master_data_width, sys_clk_freq=sys_clk_freq, spi_clk_freq=spi_master_clk_freq, ) self.add_csr("spi_master") # PWM if with_pwm: platform.add_extension([("pwm", 0, Pins(1))]) self.submodules.pwm = PWM(platform.request("pwm")) self.add_csr("pwm") # GPIO if with_gpio: platform.add_extension([("gpio", 0, Pins(gpio_width))]) self.submodules.gpio = GPIOTristate(platform.request("gpio")) self.add_csr("gpio") # Wishbone Master if kwargs["bus"] == "wishbone": wb_bus = wishbone.Interface() self.bus.add_master(master=wb_bus) platform.add_extension(wb_bus.get_ios("wb")) wb_pads = platform.request("wb") self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave") # AXI-Lite Master if kwargs["bus"] == "axi": axi_bus = axi.AXILiteInterface(data_width=32, address_width=32) wb_bus = wishbone.Interface() axi2wb = axi.AXILite2Wishbone(axi_bus, wb_bus) self.submodules += axi2wb self.bus.add_master(master=wb_bus) platform.add_extension(axi_bus.get_ios("axi")) axi_pads = platform.request("axi") self.comb += axi_bus.connect_to_pads(axi_pads, mode="slave") # IRQs for name, loc in sorted(self.irq.locs.items()): module = getattr(self, name) platform.add_extension([("irq_" + name, 0, Pins(1))]) irq_pin = platform.request("irq_" + name) self.comb += irq_pin.eq(module.ev.irq)
def __init__(self, platform, variant="standard"): self.platform = platform self.reset = Signal() self.interrupt = Signal(2) ibus = axi.AXILiteInterface(data_width=32, address_width=32) dbus = axi.AXILiteInterface(data_width=32, address_width=32) self.periph_buses = [ibus, dbus] self.memory_buses = [] # Peripheral Bus AXI <-> AXILite conversion. ibus_axi = axi.AXIInterface(data_width=self.data_width, address_width=32) self.submodules += axi.AXI2AXILite(ibus_axi, ibus) dbus_axi = axi.AXIInterface(data_width=self.data_width, address_width=32) self.submodules += axi.AXI2AXILite(dbus_axi, dbus) # CPU Instance. self.cpu_params = dict( # Clk/Rst. i_HCLK=ClockSignal("sys"), i_SYSRESETn=~(ResetSignal() | self.reset), # Control/Status. p_MPU_PRESENT=0, p_TRACE_LVL=0, p_DEBUG_LVL=2, # Interrupts. p_NUM_IRQ=len(self.interrupt), i_IRQ=self.interrupt, # Embedded ROM/SRAM. p_ITCM_SIZE=0, # Use LiteX's ROM. p_DTCM_SIZE=0, # Use LiteX's RAM. i_CFGITCMEN=0, # 1 = alias ITCM at 0x0 # Debug. i_DBGRESETn=~(ResetSignal() | self.reset), # Instruction Bus (AXI). o_AWVALIDC=ibus_axi.aw.valid, i_AWREADYC=ibus_axi.aw.ready, o_AWADDRC=ibus_axi.aw.addr, o_AWBURSTC=ibus_axi.aw.burst, o_AWCACHEC=ibus_axi.aw.cache, o_AWLENC=ibus_axi.aw.len, o_AWLOCKC=ibus_axi.aw.lock, o_AWPROTC=ibus_axi.aw.prot, o_AWSIZEC=ibus_axi.aw.size, o_WVALIDC=ibus_axi.w.valid, i_WREADYC=ibus_axi.w.ready, o_WLASTC=ibus_axi.w.last, o_WSTRBC=ibus_axi.w.strb, o_HWDATAC=ibus_axi.w.data, i_BVALIDC=ibus_axi.b.valid, o_BREADYC=ibus_axi.b.ready, i_BRESPC=ibus_axi.b.resp, o_ARVALIDC=ibus_axi.ar.valid, i_ARREADYC=ibus_axi.ar.ready, o_ARADDRC=ibus_axi.ar.addr, o_ARBURSTC=ibus_axi.ar.burst, o_ARCACHEC=ibus_axi.ar.cache, o_ARLENC=ibus_axi.ar.len, o_ARLOCKC=ibus_axi.ar.lock, o_ARPROTC=ibus_axi.ar.prot, o_ARSIZEC=ibus_axi.ar.size, i_RVALIDC=ibus_axi.r.valid, o_RREADYC=ibus_axi.r.ready, i_RLASTC=ibus_axi.r.last, i_RRESPC=ibus_axi.r.resp, i_HRDATAC=ibus_axi.r.data, # Data Bus (AXI). o_AWVALIDS=dbus_axi.aw.valid, i_AWREADYS=dbus_axi.aw.ready, o_AWADDRS=dbus_axi.aw.addr, o_AWBURSTS=dbus_axi.aw.burst, o_AWCACHES=dbus_axi.aw.cache, o_AWLENS=dbus_axi.aw.len, o_AWLOCKS=dbus_axi.aw.lock, o_AWPROTS=dbus_axi.aw.prot, o_AWSIZES=dbus_axi.aw.size, o_WVALIDS=dbus_axi.w.valid, i_WREADYS=dbus_axi.w.ready, o_WLASTS=dbus_axi.w.last, o_WSTRBS=dbus_axi.w.strb, o_HWDATAS=dbus_axi.w.data, i_BVALIDS=dbus_axi.b.valid, o_BREADYS=dbus_axi.b.ready, i_BRESPS=dbus_axi.b.resp, o_ARVALIDS=dbus_axi.ar.valid, i_ARREADYS=dbus_axi.ar.ready, o_ARADDRS=dbus_axi.ar.addr, o_ARBURSTS=dbus_axi.ar.burst, o_ARCACHES=dbus_axi.ar.cache, o_ARLENS=dbus_axi.ar.len, o_ARLOCKS=dbus_axi.ar.lock, o_ARPROTS=dbus_axi.ar.prot, o_ARSIZES=dbus_axi.ar.size, i_RVALIDS=dbus_axi.r.valid, o_RREADYS=dbus_axi.r.ready, i_RLASTS=dbus_axi.r.last, i_RRESPS=dbus_axi.r.resp, i_HRDATAS=dbus_axi.r.data, ) platform.add_source_dir( "AT426-BU-98000-r0p1-00rel0/vivado/Arm_ipi_repository/CM3DbgAXI/rtl" )
def __init__(self, sys_clk_freq=int(100e6), with_pwm=False, with_mmcm=False, with_gpio=False, gpio_width=32, with_spi_master=False, spi_master_data_width=8, spi_master_clk_freq=8e6, **kwargs): platform = Platform(_io) # UART if kwargs["with_uart"]: platform.add_extension([( "serial", 0, Subsignal("tx", Pins(1)), Subsignal("rx", Pins(1)), )]) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst")) # SoCMini ---------------------------------------------------------------------------------- print(kwargs) SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # MMCM if with_mmcm: platform.add_extension([( "clkgen", 0, Subsignal("ref", Pins(1)), Subsignal("out0", Pins(1)), Subsignal("out1", Pins(1)), Subsignal("locked", Pins(1)), )]) self.clock_domains.cd_out0 = ClockDomain(reset_less=True) self.clock_domains.cd_out1 = ClockDomain(reset_less=True) self.submodules.mmcm = mmcm = S7MMCM() mmcm.expose_drp() self.add_csr("mmcm") clkgen = platform.request("clkgen") mmcm.register_clkin(clkgen.ref, 100e6) mmcm.create_clkout(self.cd_out0, 148.5e6, with_reset=False) mmcm.create_clkout(self.cd_out1, 742.5e6, with_reset=False) self.comb += [ clkgen.out0.eq(self.cd_out0.clk), clkgen.out1.eq(self.cd_out1.clk), clkgen.locked.eq(mmcm.locked), ] # SPI Master if with_spi_master: platform.add_extension([( "spi_master", 0, Subsignal("clk", Pins(1)), Subsignal("cs_n", Pins(1)), Subsignal("mosi", Pins(1)), Subsignal("miso", Pins(1)), )]) self.submodules.spi_master = SPIMaster( pads=platform.request("spi_master"), data_width=spi_master_data_width, sys_clk_freq=sys_clk_freq, spi_clk_freq=spi_master_clk_freq, ) self.add_csr("spi_master") # PWM if with_pwm: platform.add_extension([("pwm", 0, Pins(1))]) self.submodules.pwm = PWM(platform.request("pwm")) self.add_csr("pwm") # GPIO if with_gpio: platform.add_extension([("gpio", 0, Pins(gpio_width))]) self.submodules.gpio = GPIOTristate(platform.request("gpio")) self.add_csr("gpio") # Wishbone Master if kwargs["bus"] in ["wishbone"]: wb_bus = wishbone.Interface() self.bus.add_master(master=wb_bus) platform.add_extension(wb_bus.get_ios("wb")) wb_pads = platform.request("wb") self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave") # AXI-Lite Master if kwargs["bus"] in ["axi", "axi_lite"]: axi_bus = axi.AXILiteInterface(data_width=32, address_width=32) wb_bus = wishbone.Interface() axi2wb = axi.AXILite2Wishbone(axi_bus, wb_bus) self.submodules += axi2wb self.bus.add_master(master=wb_bus) platform.add_extension(axi_bus.get_ios("axi")) axi_pads = platform.request("axi") self.comb += axi_bus.connect_to_pads(axi_pads, mode="slave") # IRQs for name, loc in sorted(self.irq.locs.items()): module = getattr(self, name) platform.add_extension([("irq_" + name, 0, Pins(1))]) irq_pin = platform.request("irq_" + name) self.comb += irq_pin.eq(module.ev.irq)
def add_soc_components(self, soc, soc_region_cls): # Set UART/Timer0 CSRs/IRQs to the ones used by OpenSBI. soc.csr.add("uart", n=2) soc.csr.add("timer0", n=3) soc.irq.add("uart", n=0) soc.irq.add("timer0", n=1) # Add OpenSBI region. soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f00000, 0x80000, type="cached+linker") # Define ISA. soc.add_constant("CPU_ISA", NaxRiscv.get_arch()) # Add PLIC Bus (AXILite Slave). self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32) self.cpu_params.update( i_peripheral_plic_awvalid=plicbus.aw.valid, o_peripheral_plic_awready=plicbus.aw.ready, i_peripheral_plic_awaddr=plicbus.aw.addr, i_peripheral_plic_awprot=Constant(2), i_peripheral_plic_wvalid=plicbus.w.valid, o_peripheral_plic_wready=plicbus.w.ready, i_peripheral_plic_wdata=plicbus.w.data, i_peripheral_plic_wstrb=plicbus.w.strb, o_peripheral_plic_bvalid=plicbus.b.valid, i_peripheral_plic_bready=plicbus.b.ready, o_peripheral_plic_bresp=plicbus.b.resp, i_peripheral_plic_arvalid=plicbus.ar.valid, o_peripheral_plic_arready=plicbus.ar.ready, i_peripheral_plic_araddr=plicbus.ar.addr, i_peripheral_plic_arprot=Constant(2), o_peripheral_plic_rvalid=plicbus.r.valid, i_peripheral_plic_rready=plicbus.r.ready, o_peripheral_plic_rdata=plicbus.r.data, o_peripheral_plic_rresp=plicbus.r.resp, ) soc.bus.add_slave("plic", self.plicbus, region=soc_region_cls(origin=soc.mem_map.get("plic"), size=0x400000, cached=False)) if NaxRiscv.jtag_tap: self.jtag_tms = Signal() self.jtag_tck = Signal() self.jtag_tdi = Signal() self.jtag_tdo = Signal() self.cpu_params.update( i_jtag_tms=self.jtag_tms, i_jtag_tck=self.jtag_tck, i_jtag_tdi=self.jtag_tdi, o_jtag_tdo=self.jtag_tdo, ) if NaxRiscv.jtag_instruction: self.jtag_clk = Signal() self.jtag_enable = Signal() self.jtag_capture = Signal() self.jtag_shift = Signal() self.jtag_update = Signal() self.jtag_reset = Signal() self.jtag_tdo = Signal() self.jtag_tdi = Signal() self.cpu_params.update( i_jtag_instruction_clk=self.jtag_clk, i_jtag_instruction_enable=self.jtag_enable, i_jtag_instruction_capture=self.jtag_capture, i_jtag_instruction_shift=self.jtag_shift, i_jtag_instruction_update=self.jtag_update, i_jtag_instruction_reset=self.jtag_reset, i_jtag_instruction_tdi=self.jtag_tdi, o_jtag_instruction_tdo=self.jtag_tdo, ) if NaxRiscv.jtag_instruction or NaxRiscv.jtag_tap: # Create PoR Clk Domain for debug_reset. self.clock_domains.cd_debug_por = ClockDomain() self.comb += self.cd_debug_por.clk.eq(ClockSignal("sys")) # Create PoR debug_reset. debug_reset = Signal(reset=1) self.sync.debug_por += debug_reset.eq(0) # Debug resets. debug_ndmreset = Signal() debug_ndmreset_last = Signal() debug_ndmreset_rise = Signal() self.cpu_params.update( i_debug_reset=debug_reset, o_debug_ndmreset=debug_ndmreset, ) # Reset SoC's CRG when debug_ndmreset rising edge. self.sync.debug_por += debug_ndmreset_last.eq(debug_ndmreset) self.comb += debug_ndmreset_rise.eq(debug_ndmreset & ~debug_ndmreset_last) self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1)) # Add CLINT Bus (AXILite Slave). self.clintbus = clintbus = axi.AXILiteInterface(address_width=32, data_width=32) self.cpu_params.update( i_peripheral_clint_awvalid=clintbus.aw.valid, o_peripheral_clint_awready=clintbus.aw.ready, i_peripheral_clint_awaddr=clintbus.aw.addr, i_peripheral_clint_awprot=Constant(2), i_peripheral_clint_wvalid=clintbus.w.valid, o_peripheral_clint_wready=clintbus.w.ready, i_peripheral_clint_wdata=clintbus.w.data, i_peripheral_clint_wstrb=clintbus.w.strb, o_peripheral_clint_bvalid=clintbus.b.valid, i_peripheral_clint_bready=clintbus.b.ready, o_peripheral_clint_bresp=clintbus.b.resp, i_peripheral_clint_arvalid=clintbus.ar.valid, o_peripheral_clint_arready=clintbus.ar.ready, i_peripheral_clint_araddr=clintbus.ar.addr, i_peripheral_clint_arprot=Constant(2), o_peripheral_clint_rvalid=clintbus.r.valid, i_peripheral_clint_rready=clintbus.r.ready, o_peripheral_clint_rdata=clintbus.r.data, o_peripheral_clint_rresp=clintbus.r.resp, ) soc.bus.add_slave("clint", clintbus, region=soc_region_cls( origin=soc.mem_map.get("clint"), size=0x10000, cached=False))
def __init__(self, sys_clk_freq=int(75e6), with_spi_flash=False, with_ethernet=False, with_etherbone=False, eth_phy=0, eth_ip="192.168.1.50", with_led_chaser=True, **kwargs): platform = efinix_trion_t120_bga576_dev_kit.Platform() # USBUART PMOD as Serial-------------------------------------------------------------------- platform.add_extension( efinix_trion_t120_bga576_dev_kit.usb_pmod_io("pmod_e")) kwargs["uart_name"] = "usb_uart" # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import W25Q128JV from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=True) platform.toolchain.excluded_ios.append( platform.lookup_request("spiflash4x").dq) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) # Tristate Test ---------------------------------------------------------------------------- from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard from litex.soc.cores.bitbang import I2CMaster platform.add_extension([( "i2c", 0, Subsignal("sda", Pins("T12")), Subsignal("scl", Pins("V11")), IOStandard("3.3_V_LVTTL_/_LVCMOS"), )]) self.submodules.i2c = I2CMaster(pads=platform.request("i2c")) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( platform=platform, clock_pads=platform.request("eth_clocks", eth_phy), pads=platform.request("eth", eth_phy), with_hw_init_reset=False) if with_ethernet: self.add_ethernet(phy=self.ethphy, software_debug=False) if with_etherbone: self.add_etherbone(phy=self.ethphy) # FIXME: Avoid this. platform.toolchain.excluded_ios.append( platform.lookup_request("eth_clocks").tx) platform.toolchain.excluded_ios.append( platform.lookup_request("eth_clocks").rx) platform.toolchain.excluded_ios.append( platform.lookup_request("eth").tx_data) platform.toolchain.excluded_ios.append( platform.lookup_request("eth").rx_data) platform.toolchain.excluded_ios.append( platform.lookup_request("eth").mdio) # LPDDR3 SDRAM ----------------------------------------------------------------------------- if not self.integrated_main_ram_size: # DRAM / PLL Blocks. # ------------------ dram_pll_refclk = platform.request("dram_pll_refclk") platform.toolchain.excluded_ios.append(dram_pll_refclk) self.platform.toolchain.additional_sdc_commands.append( f"create_clock -period {1e9/50e6} dram_pll_refclk") from litex.build.efinix import InterfaceWriterBlock, InterfaceWriterXMLBlock import xml.etree.ElementTree as et class PLLDRAMBlock(InterfaceWriterBlock): @staticmethod def generate(): return """ design.create_block("dram_pll", block_type="PLL") design.set_property("dram_pll", {"REFCLK_FREQ":"50.0"}, block_type="PLL") design.gen_pll_ref_clock("dram_pll", pll_res="PLL_BR0", refclk_src="EXTERNAL", refclk_name="dram_pll_clkin", ext_refclk_no="0") design.set_property("dram_pll","LOCKED_PIN","dram_pll_locked", block_type="PLL") design.set_property("dram_pll","RSTN_PIN","dram_pll_rst_n", block_type="PLL") design.set_property("dram_pll", {"CLKOUT0_PIN" : "dram_pll_CLKOUT0"}, block_type="PLL") design.set_property("dram_pll","CLKOUT0_PHASE","0","PLL") calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"}) """ platform.toolchain.ifacewriter.blocks.append(PLLDRAMBlock()) class DRAMXMLBlock(InterfaceWriterXMLBlock): @staticmethod def generate(root, namespaces): # CHECKME: Switch to DDRDesignService? ddr_info = root.find("efxpt:ddr_info", namespaces) ddr = et.SubElement(ddr_info, "efxpt:ddr", name="ddr_inst1", ddr_def="DDR_0", cs_preset_id="173", cs_mem_type="LPDDR3", cs_ctrl_width="x32", cs_dram_width="x32", cs_dram_density="8G", cs_speedbin="800", target0_enable="true", target1_enable="true", ctrl_type="none") gen_pin_target0 = et.SubElement(ddr, "efxpt:gen_pin_target0") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wdata", type_name=f"WDATA_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wready", type_name=f"WREADY_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wid", type_name=f"WID_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bready", type_name=f"BREADY_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rdata", type_name=f"RDATA_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aid", type_name=f"AID_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bvalid", type_name=f"BVALID_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rlast", type_name=f"RLAST_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bid", type_name=f"BID_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_asize", type_name=f"ASIZE_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_atype", type_name=f"ATYPE_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aburst", type_name=f"ABURST_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wvalid", type_name=f"WVALID_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wlast", type_name=f"WLAST_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aaddr", type_name=f"AADDR_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rid", type_name=f"RID_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_avalid", type_name=f"AVALID_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rvalid", type_name=f"RVALID_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_alock", type_name=f"ALOCK_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rready", type_name=f"RREADY_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rresp", type_name=f"RRESP_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wstrb", type_name=f"WSTRB_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aready", type_name=f"AREADY_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_alen", type_name=f"ALEN_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="axi_clk", type_name=f"ACLK_0", is_bus="false", is_clk="true", is_clk_invert="false") gen_pin_target1 = et.SubElement(ddr, "efxpt:gen_pin_target1") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wdata", type_name=f"WDATA_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wready", type_name=f"WREADY_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wid", type_name=f"WID_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bready", type_name=f"BREADY_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rdata", type_name=f"RDATA_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aid", type_name=f"AID_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bvalid", type_name=f"BVALID_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rlast", type_name=f"RLAST_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bid", type_name=f"BID_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_asize", type_name=f"ASIZE_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_atype", type_name=f"ATYPE_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aburst", type_name=f"ABURST_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wvalid", type_name=f"WVALID_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wlast", type_name=f"WLAST_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aaddr", type_name=f"AADDR_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rid", type_name=f"RID_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_avalid", type_name=f"AVALID_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rvalid", type_name=f"RVALID_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_alock", type_name=f"ALOCK_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rready", type_name=f"RREADY_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rresp", type_name=f"RRESP_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wstrb", type_name=f"WSTRB_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aready", type_name=f"AREADY_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_alen", type_name=f"ALEN_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="axi_clk", type_name=f"ACLK_1", is_bus="false", is_clk="true", is_clk_invert="false") gen_pin_config = et.SubElement(ddr, "efxpt:gen_pin_config") et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SEQ_RST", is_bus="false") et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SCL_IN", is_bus="false") et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SEQ_START", is_bus="false") et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="RSTN", is_bus="false") et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SDA_IN", is_bus="false") et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SDA_OEN", is_bus="false") cs_fpga = et.SubElement(ddr, "efxpt:cs_fpga") et.SubElement(cs_fpga, "efxpt:param", name="FPGA_ITERM", value="120", value_type="str") et.SubElement(cs_fpga, "efxpt:param", name="FPGA_OTERM", value="34", value_type="str") cs_memory = et.SubElement(ddr, "efxpt:cs_memory") et.SubElement(cs_memory, "efxpt:param", name="RTT_NOM", value="RZQ/2", value_type="str") et.SubElement(cs_memory, "efxpt:param", name="MEM_OTERM", value="40", value_type="str") et.SubElement(cs_memory, "efxpt:param", name="CL", value="RL=6/WL=3", value_type="str") timing = et.SubElement(ddr, "efxpt:cs_memory_timing") et.SubElement(timing, "efxpt:param", name="tRAS", value="42.000", value_type="float") et.SubElement(timing, "efxpt:param", name="tRC", value="60.000", value_type="float") et.SubElement(timing, "efxpt:param", name="tRP", value="18.000", value_type="float") et.SubElement(timing, "efxpt:param", name="tRCD", value="18.000", value_type="float") et.SubElement(timing, "efxpt:param", name="tREFI", value="3.900", value_type="float") et.SubElement(timing, "efxpt:param", name="tRFC", value="210.000", value_type="float") et.SubElement(timing, "efxpt:param", name="tRTP", value="10.000", value_type="float") et.SubElement(timing, "efxpt:param", name="tWTR", value="10.000", value_type="float") et.SubElement(timing, "efxpt:param", name="tRRD", value="10.000", value_type="float") et.SubElement(timing, "efxpt:param", name="tFAW", value="50.000", value_type="float") cs_control = et.SubElement(ddr, "efxpt:cs_control") et.SubElement(cs_control, "efxpt:param", name="AMAP", value="ROW-COL_HIGH-BANK-COL_LOW", value_type="str") et.SubElement(cs_control, "efxpt:param", name="EN_AUTO_PWR_DN", value="Off", value_type="str") et.SubElement(cs_control, "efxpt:param", name="EN_AUTO_SELF_REF", value="No", value_type="str") cs_gate_delay = et.SubElement(ddr, "efxpt:cs_gate_delay") et.SubElement(cs_gate_delay, "efxpt:param", name="EN_DLY_OVR", value="No", value_type="str") et.SubElement(cs_gate_delay, "efxpt:param", name="GATE_C_DLY", value="3", value_type="int") et.SubElement(cs_gate_delay, "efxpt:param", name="GATE_F_DLY", value="0", value_type="int") platform.toolchain.ifacewriter.xml_blocks.append(DRAMXMLBlock()) # DRAM Rst. # --------- dram_pll_rst_n = platform.add_iface_io("dram_pll_rst_n") self.comb += dram_pll_rst_n.eq(platform.request("user_btn", 1)) # DRAM AXI-Ports. # -------------- for n, data_width in { 0: 256, # target0: 256-bit. 1: 128, # target1: 128-bit }.items(): axi_port = axi.AXIInterface(data_width=data_width, address_width=28, id_width=8) # 256MB. ios = [( f"axi{n}", 0, Subsignal("wdata", Pins(data_width)), Subsignal("wready", Pins(1)), Subsignal("wid", Pins(8)), Subsignal("bready", Pins(1)), Subsignal("rdata", Pins(data_width)), Subsignal("aid", Pins(8)), Subsignal("bvalid", Pins(1)), Subsignal("rlast", Pins(1)), Subsignal("bid", Pins(8)), Subsignal("asize", Pins(3)), Subsignal("atype", Pins(1)), Subsignal("aburst", Pins(2)), Subsignal("wvalid", Pins(1)), Subsignal("aaddr", Pins(32)), Subsignal("rid", Pins(8)), Subsignal("avalid", Pins(1)), Subsignal("rvalid", Pins(1)), Subsignal("alock", Pins(2)), Subsignal("rready", Pins(1)), Subsignal("rresp", Pins(2)), Subsignal("wstrb", Pins(data_width // 8)), Subsignal("aready", Pins(1)), Subsignal("alen", Pins(8)), Subsignal("wlast", Pins(1)), )] io = platform.add_iface_ios(ios) rw_n = axi_port.ar.valid self.comb += [ # Pseudo AW/AR Channels. io.atype.eq(~rw_n), io.aaddr.eq(Mux(rw_n, axi_port.ar.addr, axi_port.aw.addr)), io.aid.eq(Mux(rw_n, axi_port.ar.id, axi_port.aw.id)), io.alen.eq(Mux(rw_n, axi_port.ar.len, axi_port.aw.len)), io.asize.eq(Mux(rw_n, axi_port.ar.size, axi_port.aw.size)), io.aburst.eq( Mux(rw_n, axi_port.ar.burst, axi_port.aw.burst)), io.alock.eq(Mux(rw_n, axi_port.ar.lock, axi_port.aw.lock)), io.avalid.eq( Mux(rw_n, axi_port.ar.valid, axi_port.aw.valid)), axi_port.aw.ready.eq(~rw_n & io.aready), axi_port.ar.ready.eq(rw_n & io.aready), # R Channel. axi_port.r.id.eq(io.rid), axi_port.r.data.eq(io.rdata), axi_port.r.last.eq(io.rlast), axi_port.r.resp.eq(io.rresp), axi_port.r.valid.eq(io.rvalid), io.rready.eq(axi_port.r.ready), # W Channel. io.wid.eq(axi_port.w.id), io.wstrb.eq(axi_port.w.strb), io.wdata.eq(axi_port.w.data), io.wlast.eq(axi_port.w.last), io.wvalid.eq(axi_port.w.valid), axi_port.w.ready.eq(io.wready), # B Channel. axi_port.b.id.eq(io.bid), axi_port.b.valid.eq(io.bvalid), io.bready.eq(axi_port.b.ready), ] # Connect AXI interface to the main bus of the SoC. axi_lite_port = axi.AXILiteInterface(data_width=data_width, address_width=28) self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port) self.bus.add_slave(f"target{n}", axi_lite_port, SoCRegion(origin=0x4000_0000 + 0x1000_0000 * n, size=0x1000_0000)) # 256MB. # Use DRAM's target0 port as Main Ram ----------------------------------------------------- self.bus.add_region( "main_ram", SoCRegion( origin=0x4000_0000, size=0x1000_0000, # 256MB. linker=True))
def add_soc_components(self, soc, soc_region_cls): soc.csr.add("uart", n=2) soc.csr.add("timer0", n=3) # Define ISA. soc.add_constant("CPU_ISA", NaxRiscv.get_arch()) # Add PLIC Bus (Wishbone Slave). self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32) self.cpu_params.update( i_peripheral_plic_awvalid=plicbus.aw.valid, o_peripheral_plic_awready=plicbus.aw.ready, i_peripheral_plic_awaddr=plicbus.aw.addr, i_peripheral_plic_awprot=Constant(2), i_peripheral_plic_wvalid=plicbus.w.valid, o_peripheral_plic_wready=plicbus.w.ready, i_peripheral_plic_wdata=plicbus.w.data, i_peripheral_plic_wstrb=plicbus.w.strb, o_peripheral_plic_bvalid=plicbus.b.valid, i_peripheral_plic_bready=plicbus.b.ready, o_peripheral_plic_bresp=plicbus.b.resp, i_peripheral_plic_arvalid=plicbus.ar.valid, o_peripheral_plic_arready=plicbus.ar.ready, i_peripheral_plic_araddr=plicbus.ar.addr, i_peripheral_plic_arprot=Constant(2), o_peripheral_plic_rvalid=plicbus.r.valid, i_peripheral_plic_rready=plicbus.r.ready, o_peripheral_plic_rdata=plicbus.r.data, o_peripheral_plic_rresp=plicbus.r.resp, ) soc.bus.add_slave("plic", self.plicbus, region=soc_region_cls(origin=soc.mem_map.get("plic"), size=0x400000, cached=False)) # Add CLINT Bus (Wishbone Slave). self.clintbus = clintbus = axi.AXILiteInterface(address_width=32, data_width=32) self.cpu_params.update( i_peripheral_clint_awvalid=clintbus.aw.valid, o_peripheral_clint_awready=clintbus.aw.ready, i_peripheral_clint_awaddr=clintbus.aw.addr, i_peripheral_clint_awprot=Constant(2), i_peripheral_clint_wvalid=clintbus.w.valid, o_peripheral_clint_wready=clintbus.w.ready, i_peripheral_clint_wdata=clintbus.w.data, i_peripheral_clint_wstrb=clintbus.w.strb, o_peripheral_clint_bvalid=clintbus.b.valid, i_peripheral_clint_bready=clintbus.b.ready, o_peripheral_clint_bresp=clintbus.b.resp, i_peripheral_clint_arvalid=clintbus.ar.valid, o_peripheral_clint_arready=clintbus.ar.ready, i_peripheral_clint_araddr=clintbus.ar.addr, i_peripheral_clint_arprot=Constant(2), o_peripheral_clint_rvalid=clintbus.r.valid, i_peripheral_clint_rready=clintbus.r.ready, o_peripheral_clint_rdata=clintbus.r.data, o_peripheral_clint_rresp=clintbus.r.resp, ) soc.bus.add_slave("clint", clintbus, region=soc_region_cls( origin=soc.mem_map.get("clint"), size=0x10000, cached=False))
def __init__(self, platform, variant="standard"): self.platform = platform self.reset = Signal() self.interrupt = Signal(2) pbus = axi.AXILiteInterface(data_width=32, address_width=32) self.periph_buses = [pbus] self.memory_buses = [] # Peripheral Bus AXI <-> AXILite conversion. pbus_axi = axi.AXIInterface(data_width=self.data_width, address_width=32) self.submodules += axi.AXI2AXILite(pbus_axi, pbus) # CPU Instance. self.cpu_params = dict( # Clk/Rst. i_HCLK = ClockSignal("sys"), i_SYSRESETn = ~(ResetSignal() | self.reset), # Control/Status. o_LOCKUP = Open(), o_HALTED = Open(), o_SYSRESETREQ = Open(), i_NMI = 0, i_EDBGRQ = 0, # Embedded ROM/SRAM. p_ITCM_SIZE = 0, # Use LiteX's ROM. p_DTCM_SIZE = 0, # Use LiteX's SRAM. i_CFGITCMEN = 0, # 1 = alias ITCM at 0x0 # Interrupts. p_NUM_IRQ = len(self.interrupt), i_IRQ = self.interrupt, # Debug. p_SMALL_DEBUG = True, i_DBGRESTART = 0, i_DBGRESETn = ~(ResetSignal() | self.reset), p_DEBUG_SEL = 1, # JTAG o_DBGRESTARTED = Open(), # Peripheral Bus (AXI). o_AWVALID = pbus_axi.aw.valid, i_AWREADY = pbus_axi.aw.ready, o_AWADDR = pbus_axi.aw.addr, o_AWBURST = pbus_axi.aw.burst, o_AWCACHE = pbus_axi.aw.cache, o_AWLEN = pbus_axi.aw.len, o_AWLOCK = pbus_axi.aw.lock, o_AWPROT = pbus_axi.aw.prot, o_AWSIZE = pbus_axi.aw.size, o_WVALID = pbus_axi.w.valid, i_WREADY = pbus_axi.w.ready, o_WLAST = pbus_axi.w.last, o_WSTRB = pbus_axi.w.strb, o_HWDATA = pbus_axi.w.data, i_BVALID = pbus_axi.b.valid, o_BREADY = pbus_axi.b.ready, i_BRESP = pbus_axi.b.resp, o_ARVALID = pbus_axi.ar.valid, i_ARREADY = pbus_axi.ar.ready, o_ARADDR = pbus_axi.ar.addr, o_ARBURST = pbus_axi.ar.burst, o_ARCACHE = pbus_axi.ar.cache, o_ARLEN = pbus_axi.ar.len, o_ARLOCK = pbus_axi.ar.lock, o_ARPROT = pbus_axi.ar.prot, o_ARSIZE = pbus_axi.ar.size, i_RVALID = pbus_axi.r.valid, o_RREADY = pbus_axi.r.ready, i_RLAST = pbus_axi.r.last, i_RRESP = pbus_axi.r.resp, i_HRDATA = pbus_axi.r.data, ) platform.add_source_dir("AT472-BU-98000-r0p1-00rel0/vivado/Arm_ipi_repository/CM1DbgAXI/logical/rtl")