def __init__(self, pads):
touch1 = TSTriple()
touch2 = TSTriple()
touch3 = TSTriple()
touch4 = TSTriple()
self.specials += touch1.get_tristate(pads.t1)
self.specials += touch2.get_tristate(pads.t2)
self.specials += touch3.get_tristate(pads.t3)
self.specials += touch4.get_tristate(pads.t4)
self.o = CSRStorage(size=4)
self.oe = CSRStorage(size=4)
self.i = CSRStatus(size=4)
self.comb += [
touch1.o.eq(self.o.storage[0]),
touch2.o.eq(self.o.storage[1]),
touch3.o.eq(self.o.storage[2]),
touch4.o.eq(self.o.storage[3]),
touch1.oe.eq(self.oe.storage[0]),
touch2.oe.eq(self.oe.storage[1]),
touch3.oe.eq(self.oe.storage[2]),
touch4.oe.eq(self.oe.storage[3]),
self.i.status.eq(Cat(touch1.i, touch2.i, touch3.i, touch4.i))
]
def __init__(self, parent, offsets=None):
table = ""
if offsets is not None:
arr = [["Image", "Offset"]]
for i, offset in enumerate(offsets):
arr.append([str(i), str(offset)])
table = "\nYou can use this block to reboot into one of these four addresses:\n\n" \
+ lxsocdoc.rst.make_table(arr)
self.intro = ModuleDoc("""FPGA Reboot Interface
This module provides the ability to reboot the FPGA. It is based on the
``SB_WARMBOOT`` primitive built in to the FPGA.
When power is applied to the FPGA, it reads configuration data from the
onboard flash chip. This contains reboot offsets for four images. It then
booted from the first image, but kept note of the other addresses.
{}""".format(table))
self.ctrl = CSRStorage(fields=[
CSRField("image",
size=2,
description="""
Which image to reboot to. ``SB_WARMBOOT`` supports four images that
are configured at FPGA startup. The bootloader is image 0, so set
these bits to 0 to reboot back into the bootloader.
"""),
CSRField("key",
size=6,
description="""
A reboot key used to prevent accidental reboots when writing to random
areas of memory. To initiate a reboot, set this to ``0b101011``."""
)
],
description="""
Provides support for rebooting the FPGA. You can select which of the four images
to reboot to, just be sure to OR the image number with ``0xac``. For example,
to reboot to the bootloader (image 0), write ``0xac``` to this register."""
)
self.addr = CSRStorage(size=32,
description="""
This sets the reset vector for the VexRiscv. This address will be used whenever
the CPU is reset, for example through a debug bridge. You should update this
address whenever you load a new program, to enable the debugger to run ``mon reset``
""")
do_reset = Signal()
self.comb += [
# "Reset Key" is 0xac (0b101011xx)
do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3]
& ~self.ctrl.storage[4]
& self.ctrl.storage[5] & ~self.ctrl.storage[6]
& self.ctrl.storage[7])
]
self.specials += Instance(
"SB_WARMBOOT",
i_S0=self.ctrl.storage[0],
i_S1=self.ctrl.storage[1],
i_BOOT=do_reset,
)
parent.config["BITSTREAM_SYNC_HEADER1"] = 0x7e99aa7e
parent.config["BITSTREAM_SYNC_HEADER2"] = 0x7eaa997e
def __init__(self, D, dst_ip="192.168.1.100"):
'''
D must be >= phy datapath width
send UDP packets with content
08 07 06 05 04 03 02 01 for n_words - 1 times
64 bit sequence number
'''
self.source = source = stream.Endpoint(eth_udp_user_description(D * 8))
###
seq = Signal(64)
timer = Signal(32)
cur_word = Signal(16, reset=1)
self.period = CSRStorage(32, reset=0x1FFFFFFF)
self.dst_ip = CSRStorage(
32,
reset=convert_ip(dst_ip),
description='Destination IP address for UDP stream')
self.dst_port = CSRStorage(16,
reset=1337,
description='Destination port number')
self.n_words = CSRStorage(
16, reset=4, description='Number of D-bit words in the paket')
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
self.fsm.act(
"IDLE", NextValue(timer, timer + 1),
If((self.period.storage > 0) & (timer >= self.period.storage),
NextValue(timer, 0), NextState("SEND")))
fsm.act(
"SEND",
source.valid.eq(1),
source.src_port.eq(self.dst_port.storage),
source.dst_port.eq(self.dst_port.storage),
source.ip_address.eq(self.dst_ip.storage),
source.length.eq(self.n_words.storage * D), # payload length
If(
cur_word == 1,
source.data.eq(seq),
).Else(source.data.eq(0x0807060504030201)),
If(
cur_word >= self.n_words.storage,
source.last.eq(1),
# last_be indicates that this byte is the first one
# which is no longer valid
# if all bytes are valid in the last cycle,
# set last=1 and last_be=0
source.last_be.eq(0x80),
If(
source.ready,
NextValue(cur_word, 1),
NextValue(seq, seq + 1),
NextState("IDLE"),
),
).Else(If(source.ready, NextValue(cur_word, cur_word + 1))),
)
def add_csr(self):
self.ddc_deci = CSRStorage(len(self.cic_period), reset=48, name="deci")
self.ddc_shift = CSRStorage(len(self.cic_shift), reset=0, name="shift")
self.specials += [
MultiReg(self.ddc_deci.storage, self.cic_period, 'sample'),
MultiReg(self.ddc_shift.storage, self.cic_shift, 'sample')
]
self.dds.add_csr()
def __init__(self, rgb_pins):
self.r = CSRStorage(8, reset=255)
self.g = CSRStorage(8)
self.b = CSRStorage(8)
self._div_m = CSRStorage(32)
self._config = CSRStorage(
1,
fields=[
CSRField('breath',
size=1,
description='Modulate output with a breath effect'),
CSRField('rainbow',
size=1,
description='Modulate output with rainbow'),
])
div_m_counter = Signal(32)
strobe = Signal()
self.sync += [
If(
div_m_counter >= self._div_m.storage,
div_m_counter.eq(0),
).Else(div_m_counter.eq(div_m_counter + 1))
]
# Activate strobe on counter rollover if counter is enabled.
self.comb += strobe.eq((div_m_counter == 0)
& (self._div_m.storage != 0))
self.submodules.pdm_r = PDM(16)
self.submodules.pdm_g = PDM(16)
self.submodules.pdm_b = PDM(16)
self.submodules.pwm0 = PWM(16, strobe, 1 << 0)
modulate = Signal()
self.comb += modulate.eq(
Mux(self._config.fields.breath, self.pwm0.out, 1))
self.comb += [
rgb_pins.r.eq(~(self.pdm_r.out & modulate)),
rgb_pins.g.eq(~(self.pdm_g.out & modulate)),
rgb_pins.b.eq(~(self.pdm_b.out & modulate)),
]
self.comb += [
self.pdm_r.level.eq(self.r.storage),
self.pdm_g.level.eq(self.g.storage),
self.pdm_b.level.eq(self.b.storage)
]
def __init__(self, sys_clk_freq, o_pwm):
self.duty = CSRStorage(8)
self.enable = CSRStorage()
self.submodules.pwm = _PWM(sys_clk_freq)
self.comb += o_pwm.eq(self.pwm.o_pwm)
self.sync += [
self.pwm.i_duty.eq(self.duty.storage),
self.pwm.i_enable.eq(self.enable.storage)
]
def add_csrs(self):
super().add_csrs()
self._error_count = CSRStatus(size=len(self.error_count),
description='Number of errors detected')
self._skip_fifo = CSRStorage(
description='Skip waiting for user to read the errors FIFO')
self._error_offset = CSRStatus(
size=len(self.mem_mask), description='Current offset of the error')
self._error_data = CSRStatus(
size=len(self.data_port.dat_r),
description='Erroneous value read from DRAM memory')
self._error_expected = CSRStatus(
size=len(self.data_port.dat_r),
description='Value expected to be read from DRAM memory')
self._error_ready = CSRStatus(
description='Error detected and ready to read')
self._error_continue = CSR()
self._error_continue.description = 'Continue reading until the next error'
self.comb += [
self._error_count.status.eq(self.error_count),
self.skip_fifo.eq(self._skip_fifo.storage),
self._error_offset.status.eq(self.error.offset),
self._error_data.status.eq(self.error.data),
self._error_expected.status.eq(self.error.expected),
self.error.ready.eq(self._error_continue.re),
self._error_ready.status.eq(self.error.valid),
]
def add_csrs(self):
self._refresh_count = CSRStatus(
len(self.refresh_counter.counter),
description=
"Count of all refresh commands issued (both by Memory Controller and Payload Executor)."
" Value is latched from internal counter on mode trasition: MC -> PE or by writing to"
" the `refresh_update` CSR.")
self._at_refresh = CSRStorage(
len(self.at_refresh),
reset=0,
description=
"If set to a value different than 0 the mode transition MC -> PE will be peformed only"
" when the value of this register matches the current refresh commands count."
)
self._refresh_update = CSR()
self._refresh_update.description = "Force an update of the `refresh_count` CSR."
self.comb += self.at_refresh.eq(self._at_refresh.storage)
# detect mode transition
pe_ongoing = self.fsm.ongoing("PAYLOAD-EXECUTION")
mc_ongoing = self.fsm.ongoing("MEMORY-CONTROLLER")
mc_ongoing_d = Signal()
self.sync += mc_ongoing_d.eq(mc_ongoing)
mc_to_pe = mc_ongoing_d & pe_ongoing
self.sync += If(
mc_to_pe | self._refresh_update.re,
self._refresh_count.status.eq(self.refresh_counter.counter),
)
def add_csrs(self):
self._divisor_mask = CSRStorage(
len(self.selector.divisor_mask),
description=
"Divisor mask for selecting rows for which pattern data gets inverted"
)
self._selection_mask = CSRStorage(
len(self.selector.selection_mask),
description=
"Selection mask for selecting rows for which pattern data gets inverted"
)
self.comb += [
self.selector.divisor_mask.eq(self._divisor_mask.storage),
self.selector.selection_mask.eq(self._selection_mask.storage),
]
def add_csr(self):
# Reference phase multiplication factors
for i, multf in enumerate(self.mult_factors):
n = 'mult{}'.format(i + 1)
csr = CSRStorage(len(multf), reset=1, name=n)
setattr(self, n, csr)
self.specials += MultiReg(csr.storage, multf, 'sample')
def __init__(self, parent):
self.ctrl = CSRStorage(size=8)
self.addr = CSRStorage(size=32)
do_reset = Signal()
self.comb += [
# "Reset Key" is 0xac (0b101011xx)
do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3] & ~self.ctrl.storage[4]
& self.ctrl.storage[5] & ~self.ctrl.storage[6] & self.ctrl.storage[7])
]
self.specials += Instance("SB_WARMBOOT",
i_S0 = self.ctrl.storage[0],
i_S1 = self.ctrl.storage[1],
i_BOOT = do_reset,
)
parent.config["BITSTREAM_SYNC_HEADER1"] = 0x7e99aa7e
parent.config["BITSTREAM_SYNC_HEADER2"] = 0x7eaa997e
def __init__(self, pads):
rgba_pwm = Signal(3)
self.dat = CSRStorage(8)
self.addr = CSRStorage(4)
self.ctrl = CSRStorage(4)
self.specials += Instance("SB_RGBA_DRV",
i_CURREN = self.ctrl.storage[1],
i_RGBLEDEN = self.ctrl.storage[2],
i_RGB0PWM = rgba_pwm[0],
i_RGB1PWM = rgba_pwm[1],
i_RGB2PWM = rgba_pwm[2],
o_RGB0 = pads.rgb0,
o_RGB1 = pads.rgb1,
o_RGB2 = pads.rgb2,
p_CURRENT_MODE = "0b1",
p_RGB0_CURRENT = "0b000011",
p_RGB1_CURRENT = "0b000001",
p_RGB2_CURRENT = "0b000011",
)
self.specials += Instance("SB_LEDDA_IP",
i_LEDDCS = self.dat.re,
i_LEDDCLK = ClockSignal(),
i_LEDDDAT7 = self.dat.storage[7],
i_LEDDDAT6 = self.dat.storage[6],
i_LEDDDAT5 = self.dat.storage[5],
i_LEDDDAT4 = self.dat.storage[4],
i_LEDDDAT3 = self.dat.storage[3],
i_LEDDDAT2 = self.dat.storage[2],
i_LEDDDAT1 = self.dat.storage[1],
i_LEDDDAT0 = self.dat.storage[0],
i_LEDDADDR3 = self.addr.storage[3],
i_LEDDADDR2 = self.addr.storage[2],
i_LEDDADDR1 = self.addr.storage[1],
i_LEDDADDR0 = self.addr.storage[0],
i_LEDDDEN = self.dat.re,
i_LEDDEXE = self.ctrl.storage[0],
# o_LEDDON = led_is_on, # Indicates whether LED is on or not
# i_LEDDRST = ResetSignal(), # This port doesn't actually exist
o_PWMOUT0 = rgba_pwm[0],
o_PWMOUT1 = rgba_pwm[1],
o_PWMOUT2 = rgba_pwm[2],
o_LEDDON = Signal(),
)
def __init__(self):
self.ctrl = CSRStorage(size=8)
self.addr = CSRStorage(size=32)
do_reset = Signal()
self.comb += [
# "Reset Key" is 0xac (0b101011xx)
do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3]
& ~self.ctrl.storage[4]
& self.ctrl.storage[5] & ~self.ctrl.storage[6]
& self.ctrl.storage[7])
]
self.specials += Instance(
"SB_WARMBOOT",
i_S0=self.ctrl.storage[0],
i_S1=self.ctrl.storage[1],
i_BOOT=do_reset,
)
def __init__(self, pin):
self.ctrl = CSRStorage(
8, description="Write ``0xac`` here to reboot the device")
self.intro = ModuleDoc(title="Reboot Control",
body="""
Access reboot control for the badge. Write the key to ``reboot`` in
order to initiate a reboot.""")
self.comb += If(self.ctrl.storage != 0xac, pin.eq(1))
def __init__(self, pads):
self.alt_fields = ["csr_control"]
pins = [0, 1, 5, 6, 9, 10, 11, 12, 13, 18, 19, 20, 21]
nbits = len(pins)
fields = []
for n in pins:
fields += [
CSRField(f"io{n}",
1,
n,
description=f"Control for I/O pin {n}"),
]
self._oe = CSRStorage(nbits,
description="""GPIO Tristate(s) Control.
Write ``1`` enable output driver""",
fields=fields)
self._in = CSRStatus(nbits,
description="""GPIO Input(s) Status.
Input value of IO pad as read by the FPGA""",
fields=fields)
self._out = CSRStorage(nbits,
description="""GPIO Ouptut(s) Control.
Value loaded into the output driver""",
fields=fields)
# # #
self._io = []
for n, p in zip(pins, pads):
m = IOPin(p)
# Create a connection to the CSR
alt_csr = io_pins()
self.comb += [
alt_csr.o.eq(self._out.storage[n]),
alt_csr.oe.eq(self._oe.storage[n]),
self._in.status.eq(alt_csr.i)
]
m.add_alt(alt_csr)
self.submodules += m
self._io += [(n, m)]
def __init__(self):
self.submodules.fifo = f = fifo.SyncFIFOBuffered(width=8, depth=64)
in_reg = CSRStorage(8,
name="in",
description="""
Write half of the FIFO to send data out the Messible.
Writing to this register advances the write pointer automatically."""
)
out_reg = CSRStatus(8,
name="out",
description="""
Read half of the FIFO to receive data on the Messible.
Reading from this register advances the read pointer automatically."""
)
self.__setattr__("in", in_reg)
self.__setattr__("out", out_reg)
self.status = status = CSRStatus(fields=[
CSRField(
"full",
description="``0`` if more data can fit into the IN FIFO."),
CSRField(
"have",
description="``1`` if data can be read from the OUT FIFO."),
])
self.intro = ModuleDoc("""
Messible: An Ansible for Messages
An Ansible is a system for instant communication across vast distances, from
a small portable device to a huge terminal far away. A Messible is a message-
passing system from embedded devices to a host system. You can use it to get
very simple printf()-style support over a debug channel.
The Messible assumes the host has a way to peek into the device's memory space.
This is the case with the Wishbone bridge, which allows both the device and
the host to access the same memory.
At its core, a Messible is a FIFO. As long as the ``STATUS.FULL`` bit is ``0``, the
device can write data into the Messible by writing into the ``IN``. However, if this
value is ``1``, you need to decide if you want to wait for it to empty (if the other
side is just slow), or if you want to drop the message.
From the host side, you need to read ``STATUS.HAVE`` to see if there is data
in the FIFO. If there is, read ``OUT`` to get the most recent byte, which automatically
advances the ``READ`` pointer.
""")
self.comb += [
f.din.eq(in_reg.storage),
f.we.eq(in_reg.re),
out_reg.status.eq(f.dout),
f.re.eq(out_reg.we),
status.fields.full.eq(~f.writable),
status.fields.have.eq(f.readable),
]
def __init__(self):
self.wishbone = wishbone.Interface()
self._start = CSRStorage(fields=[CSRField("start_burst", size=1, offset=0, pulse=True)])
self._ready = CSRStatus(8)
self._burst_size = CSRStorage(16)
self._base = CSRStorage(32)
self._offset = CSRStorage(32)
words_count = Signal(16)
pass_count = Signal(5)
self.wb_dma = wb_dma = WishboneDMAWriter(self.wishbone, endianness="big")
self.submodules += wb_dma
self.comb += [
self.wb_dma.sink.address.eq((self._base.storage >> 2) + (self._offset.storage>>2) + words_count),
self.wb_dma.sink.data.eq(pass_count),
]
fsm = FSM(reset_state="WAIT-FOR-TRIGGER")
self.submodules += fsm
fsm.act("WAIT-FOR-TRIGGER",
self._ready.status.eq(1),
NextValue(words_count, 0),
If(self._start.fields.start_burst,
NextState("WRITE-DATA"),
)
)
fsm.act("WRITE-DATA",
self.wb_dma.sink.valid.eq(1),
If(self.wb_dma.sink.ready,
NextValue(words_count, words_count+1),
If(words_count == (self._burst_size.storage-1),
NextState("WAIT-FOR-TRIGGER"),
NextValue(pass_count, pass_count+1)
)
)
)
def __init__(self, dma):
address_width = len(dma.sink.address)
self.enabled = CSRStorage(
description="Used to start/stop the operation of the module")
self.address1 = CSRStorage(address_width,
description="First attacked address")
self.address2 = CSRStorage(address_width,
description="Second attacked address")
self.count = CSRStatus(
32,
description="""This is the number of DMA accesses performed.
When the module is enabled, the value can be freely read. When
the module is disabled, the register is clear-on-write and has
to be read before the next attack.""")
counter = Signal.like(self.count.status)
self.comb += self.count.status.eq(counter)
self.sync += \
If(self.enabled.storage,
If(dma.sink.valid & dma.sink.ready,
counter.eq(counter + 1)
)
).Elif(self.count.we, # clear on read when not enabled
counter.eq(0)
)
address = Signal(address_width)
self.comb += Case(
counter[0], {
0: address.eq(self.address1.storage),
1: address.eq(self.address2.storage),
})
self.comb += [
dma.sink.address.eq(address),
dma.sink.valid.eq(self.enabled.storage),
dma.source.ready.eq(1),
]
def __init__(self, platform, pads):
self.reset = Signal()
mosi_pad = TSTriple()
miso_pad = TSTriple()
cs_n_pad = TSTriple()
clk_pad = TSTriple()
wp_pad = TSTriple()
hold_pad = TSTriple()
self.do = CSRStorage(size=6)
self.oe = CSRStorage(size=6)
self.di = CSRStatus(size=6)
self.specials += mosi_pad.get_tristate(pads.mosi)
self.specials += miso_pad.get_tristate(pads.miso)
self.specials += cs_n_pad.get_tristate(pads.cs_n)
self.specials += clk_pad.get_tristate(pads.clk)
self.specials += wp_pad.get_tristate(pads.wp)
self.specials += hold_pad.get_tristate(pads.hold)
self.comb += [
mosi_pad.oe.eq(self.oe.storage[0]),
miso_pad.oe.eq(self.oe.storage[1]),
wp_pad.oe.eq(self.oe.storage[2]),
hold_pad.oe.eq(self.oe.storage[3]),
clk_pad.oe.eq(self.oe.storage[4]),
cs_n_pad.oe.eq(self.oe.storage[5]),
mosi_pad.o.eq(self.do.storage[0]),
miso_pad.o.eq(self.do.storage[1]),
wp_pad.o.eq(self.do.storage[2]),
hold_pad.o.eq(self.do.storage[3]),
clk_pad.o.eq(self.do.storage[4]),
cs_n_pad.o.eq(self.do.storage[5]),
self.di.status.eq(
Cat(mosi_pad.i, miso_pad.i, wp_pad.i, hold_pad.i, clk_pad.i,
cs_n_pad.i)),
]
def add_csrs(self):
self._start = CSR()
self._start.description = 'Write to the register starts the transfer (if ready=1)'
self._ready = CSRStatus(
description='Indicates that the transfer is not ongoing')
self._count = CSRStorage(size=len(self.count),
description='Desired number of DMA transfers')
self._done = CSRStatus(size=len(self.done),
description='Number of completed DMA transfers')
self._mem_mask = CSRStorage(
size=len(self.mem_mask),
description='DRAM address mask for DMA transfers')
self._data_mask = CSRStorage(size=len(self.mem_mask),
description='Pattern memory address mask')
self.comb += [
self.start.eq(self._start.re),
self._ready.status.eq(self.ready),
self.count.eq(self._count.storage),
self._done.status.eq(self.done),
self.mem_mask.eq(self._mem_mask.storage),
self.data_mask.eq(self._data_mask.storage),
]
def __init__(self, pads):
self.intro = ModuleDoc("""Fomu Touchpads
Fomu has four single-ended exposed pads on its side. These pads are designed
to be connected to some captouch block, or driven in a resistive touch mode
in order to get simple touchpad support.
This block simply provides CPU-controlled GPIO support for this block. It has
three registers which control the In, Out, and Output Enable functionality of
each of these pins.
""")
touch1 = TSTriple()
touch2 = TSTriple()
touch3 = TSTriple()
touch4 = TSTriple()
self.specials += touch1.get_tristate(pads.t1)
self.specials += touch2.get_tristate(pads.t2)
self.specials += touch3.get_tristate(pads.t3)
self.specials += touch4.get_tristate(pads.t4)
self.o = CSRStorage(4, description="Output values for pads 1-4")
self.oe = CSRStorage(4,
description="Output enable control for pads 1-4")
self.i = CSRStatus(4, description="Input value for pads 1-4")
self.comb += [
touch1.o.eq(self.o.storage[0]),
touch2.o.eq(self.o.storage[1]),
touch3.o.eq(self.o.storage[2]),
touch4.o.eq(self.o.storage[3]),
touch1.oe.eq(self.oe.storage[0]),
touch2.oe.eq(self.oe.storage[1]),
touch3.oe.eq(self.oe.storage[2]),
touch4.oe.eq(self.oe.storage[3]),
self.i.status.eq(Cat(touch1.i, touch2.i, touch3.i, touch4.i))
]
def __init__(self, pads, gpio_name):
nbits = len(pads)
fields = [CSRField(fld[0], description=fld[1]) for fld in gpio_name]
self._oe = CSRStorage(nbits,
description="GPIO Tristate(s) Control.",
fields=fields)
self._in = CSRStatus(nbits,
description="GPIO Input(s) Status.",
fields=fields)
self._out = CSRStorage(nbits,
description="GPIO Output(s) Control.",
fields=fields)
# # #
_pads = Signal(nbits)
self.comb += _pads.eq(pads)
for i in range(nbits):
t = TSTriple()
self.specials += t.get_tristate(_pads[i])
self.comb += t.oe.eq(self._oe.storage[i])
self.comb += t.o.eq(self._out.storage[i])
self.specials += MultiReg(t.i, self._in.status[i])
def __init__(self, pads):
self.output = CSRStorage(3)
self.specials += Instance("SB_RGBA_DRV",
i_CURREN = 0b1,
i_RGBLEDEN = 0b1,
i_RGB0PWM = self.output.storage[0],
i_RGB1PWM = self.output.storage[1],
i_RGB2PWM = self.output.storage[2],
o_RGB0 = pads.r,
o_RGB1 = pads.g,
o_RGB2 = pads.b,
p_CURRENT_MODE = "0b1",
p_RGB0_CURRENT = "0b000011",
p_RGB1_CURRENT = "0b000011",
p_RGB2_CURRENT = "0b000011",
)
def __init__(
self,
ppm_pad,
servo_pads=None,
ppm_dev=None,
channels=8,
frequency=50,
clk_period=1e9/16e6,
resolution=1e3,
pulse_width=300e3,
max_width=2000e3,
min_width=1000e3,
csr_width=8,
alignment=2,
):
if ppm_dev == None:
self.submodules.ppm_dev = ppm.PPMoutput(
channels=channels,
frequency=frequency,
clk_period=clk_period,
resolution=resolution,
pulse_width=pulse_width,
max_width=max_width,
min_width=min_width
)
else:
self.ppm_dev = ppm_dev
channels = self.ppm_dev.channels
self.widths = []
for chan in range(channels):
tmp = CSRStorage(csr_width, name='channel_'+str(chan))
self.widths.append(tmp)
setattr(self, f"tmp{chan}", tmp)
# assign an input pin to the PPM device
self.comb += ppm_pad.eq(self.ppm_dev.ppm)
for chan in range(channels):
ppm_size = self.ppm_dev.widths[chan].nbits
if csr_width >= ppm_size:
self.comb += self.ppm_dev.widths[chan].eq(self.widths[chan].storage[:ppm_size])
else:
self.comb += self.ppm_dev.widths[chan][alignment:csr_width+alignment].eq(self.widths[chan].storage)
self.comb += self.ppm_dev.widths[chan][:alignment].eq(0)
if servo_pads != None:
self.comb += servo_pads[chan].eq(self.ppm_dev.pwm[chan])
def csr_helper(obj, name, regs, cdc=False, pulsed=False, **kwargs):
'''
handle csr + optional clock domain crossing (cdc) from sys to sample
obj: the object where the csr will be pushed into
cdc: add a pulse synchronizer to move the csr write strobe to the
sample domain, then use the strobe to latch csr.storage
pulsed: instead of latching csr.storage in the sample clock domain,
make its value valid only for one cycle and zero otherwise
'''
if type(regs) not in (list, tuple):
regs = [regs]
for i, reg in enumerate(regs):
name_ = name
if len(regs) > 1:
name_ += str(i)
if 'reset' not in kwargs:
try:
kwargs['reset'] = reg.reset
except AttributeError:
print('csr_helper(): could not extract reset value from',
name_, reg)
csr = CSRStorage(len(reg), name=name_, **kwargs)
print('CSR: {} len({}) reset({})'.format(csr.name, len(csr.storage),
csr.storage.reset.value))
setattr(obj, name_, csr)
if cdc:
# csr.storage is fully latched and stable when csr.re is pulsed
# hence we only need to cross the csr.re pulse into the sample
# clock domain and then latch csr.storage there once more
ps = PulseSynchronizer('sys', 'sample')
setattr(obj.submodules, name_ + '_sync', ps)
obj.comb += ps.i.eq(csr.re)
if pulsed:
obj.sync.sample += reg.eq(Mux(ps.o, csr.storage, 0))
else:
obj.sync.sample += If(ps.o, reg.eq(csr.storage))
else:
if pulsed:
obj.comb += reg.eq(Mux(csr.re, csr.storage, 0))
else:
obj.comb += reg.eq(csr.storage)
def add_csr(self, f_sys, p):
''' Wire up the config-registers to litex CSRs '''
self.ddc.add_csr()
self.pp.add_csr()
self.pulse.add_csr()
# sys clock domain
n_ch = len(self.adcs)
self.mags_sys = [Signal.like(self.mags_iir[0]) for i in range(n_ch)]
self.phases_sys = [
Signal.like(self.phases_iir[0]) for i in range(n_ch)
]
# Clock domain crossing on self.strobe_
self.submodules.cdc = BlindTransfer("sample", "sys",
n_ch * (self.W_MAG + self.W_PHASE))
# IIR controls
self.iir = CSRStorage(len(self.iir_shift))
self.specials += MultiReg(self.iir.storage, self.iir_shift, 'sample')
self.comb += [
self.cdc.data_i.eq(Cat(self.mags_iir + self.phases_iir)),
self.cdc.i.eq(self.strobe_out),
Cat(self.mags_sys + self.phases_sys).eq(self.cdc.data_o)
]
# CSRs for peeking at phase / magnitude values
for i, sig in enumerate(self.mags_sys + self.phases_sys):
if i <= 3:
n = 'mag{:d}'.format(i)
else:
n = 'phase{:d}'.format(i - 4)
csr = CSRStatus(32, name=n)
setattr(self, n, csr)
self.specials += MultiReg(sig, csr.status)
# Frequency counters for the ADC inputs
for i, adc in enumerate(self.adcs):
zc = ZeroCrosser(int(100e6))
self.comb += zc.sig_in.eq(adc > 0)
zc.add_csr()
setattr(self.submodules, 'zc{}'.format(i), zc)
def finalize(self):
# create Alt fields
values = []
for i, n in zip(range(len(self.alt_fields)), self.alt_fields):
values += [(i, n)]
f = CSRField("ctrl",
size=8,
description="Select alternative function on IO pin",
values=values)
for n, m in self._io:
csr = CSRStorage(8,
name=f"alt{n}",
description="""GPIO Alt Control.
IO pin alternative functions""",
fields=[f])
setattr(self, f"_alt{n}", csr)
self.comb += m.alt.eq(csr.storage)
def __init__(self, width, depth, port, **kwargs):
self.adc_data = adc_data = Signal(width)
acq_start, acq_start_x = Signal(reset=0), Signal(reset=0)
self._buf_full = CSRStatus(
fields=[CSRField("acq_complete", size=1, offset=0)])
self._acq_start = CSRStorage(
fields=[CSRField("acq_start", size=1, offset=0, pulse=True)])
w_addr = Signal(16, reset=0)
self.comb += [
self._buf_full.fields.acq_complete.eq(w_addr == depth),
acq_start.eq(self._acq_start.fields.acq_start),
port.adr.eq(w_addr),
port.dat_w.eq(adc_data),
port.we.eq(w_addr != depth)
]
self.submodules.ps = PulseSynchronizer("sys", "sample")
self.comb += [self.ps.i.eq(acq_start), acq_start_x.eq(self.ps.o)]
self.sync.sample += [
If(acq_start_x & (w_addr == depth),
w_addr.eq(0)).Elif(w_addr != depth, w_addr.eq(w_addr + 1))
]
def __init__(self):
# self.counter = Signal(8)
# self.test_value = CSR(8)
# self.result = Signal(8)
# self.read_result = Signal()
# self.sync += [
# self.counter.eq(self.counter+1),
# self.test_value.w.eq(self.counter),
# self.result.eq(self.test_value.r),
# self.read_result.eq(self.test_value.re),
# ]
self.counter = Signal(8)
self.test_value = CSRStorage(8, write_from_dev=True)
self.result = Signal(8)
self.result_re = Signal()
self.sync += [
self.counter.eq(self.counter + 1),
self.test_value.we.eq(1),
self.test_value.dat_w.eq(self.counter),
self.result.eq(self.test_value.storage),
self.result_re.eq(self.test_value.re),
]
def __init__(self, pads):
_fields_input = [
CSRField("MODPRSL"),
CSRField("INTL"),
]
_fields_output = [
CSRField("MODSELL", reset=1),
CSRField("RESETL", reset=1),
CSRField("LPMODE", reset=0),
]
self.status = status = CSRStatus(fields=_fields_input,
name="qsfp0_status")
self.control = control = CSRStorage(fields=_fields_output,
name="qsfp0_control")
for _f in _fields_input:
self.comb += getattr(status.fields,
_f.name).eq(getattr(pads, _f.name))
for _f in _fields_output:
self.comb += getattr(pads,
_f.name).eq(getattr(control.fields, _f.name))
