def __init__(self, board, revision, sys_clk_freq=60e6, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_phy=0, use_internal_osc=False, sdram_rate="1:1", **kwargs):
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
if board == "5a-75e" and revision == "6.0" and (with_etherbone or with_ethernet):
assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset."
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, int(sys_clk_freq),
ident = "LiteX SoC on Colorlight " + board.upper(),
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll,with_rst=with_rst, sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
if board == "5a-75e" and revision == "6.0":
sdram_cls = M12L64322A
sdram_size = 0x80000000
else:
sdram_cls = M12L16161A
sdram_size = 0x40000000
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdram_cls(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", sdram_size),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy),
tx_delay = 0e-9)
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Leds -------------------------------------------------------------------------------------
if platform.lookup_request("serial", loose=True) is None: # Disable leds when serial is used.
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self, revision):
platform = colorlight_5a_75e.Platform(revision)
sys_clk_freq = int(25e6)
platform.add_extension(_serial)
platform.add_extension(_leds)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="vexriscv",
clk_freq=25e6,
ident="LiteX CPU Test SoC 5A-75E",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk25"),
~platform.request("user_btn_n"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(2)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
def __init__(self,
board,
revision,
with_ethernet=False,
with_etherbone=False,
sys_clk_freq=60e6,
sdram_rate="1:1",
**kwargs):
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Colorlight " + board.upper(),
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in [
"serial", "bridge"
] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_usb_pll=with_usb_pll,
with_rst=with_rst,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L16161A(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
def __init__(self, revision, with_ethernet=False, with_etherbone=False, sys_clk_freq=60e6, **kwargs):
platform = colorlight_5a_75e.Platform(revision=revision)
if (with_etherbone):
sys_clk_freq = int(125e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll=with_usb_pll,with_rst=with_rst)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy = self.sdrphy,
module = M12L16161A(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
def __init__(self,
debug,
flash_offset,
board,
revision,
with_ethernet=False,
with_etherbone=False,
eth_phy=0,
sys_clk_freq=60e6,
use_internal_osc=False,
sdram_rate="1:1",
**kwargs):
"""Create a basic SoC for Colorlight 5A-75X.
Returns:
Newly-constructed SoC
"""
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
if board == "5a-75e" and revision == "6.0" and (with_etherbone
or with_ethernet):
assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset."
# Set cpu name and variant defaults when none are provided
if "cpu_variant" not in kwargs:
if debug:
kwargs["cpu_variant"] = "imac+debug"
else:
kwargs["cpu_variant"] = "imac"
kwargs["integrated_main_ram_size"] = 0
kwargs["integrated_rom_size"] = 0
kwargs["csr_data_width"] = 32
# Set CPU reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + flash_offset
# Select "crossover" as soc uart instead of "serial"
# We have to make that selection before calling the parent initializer
if debug:
kwargs["uart_name"] = "crossover"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
int(sys_clk_freq),
ident="LiteX SoC on Colorlight " + board.upper(),
ident_version=True,
**kwargs)
with_rst = kwargs["uart_name"] not in [
"serial", "bridge", "crossover"
] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform,
sys_clk_freq,
use_internal_osc=use_internal_osc,
with_usb_pll=with_usb_pll,
with_rst=with_rst,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
if board == "5a-75e" and revision == "6.0":
sdram_cls = M12L64322A
sdram_size = 0x80000000
else:
sdram_cls = M12L16161A
sdram_size = 0x40000000
self.add_sdram("sdram",
phy=self.sdrphy,
module=sdram_cls(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", sdram_size),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spiflash_size = 32 * 1024 * 1024
self.submodules.spiflash = spiflash = SpiFlash(
platform.request("spiflash"), dummy=8, endianness="little")
spiflash.add_clk_primitive(platform.device)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=spiflash_size)
self.add_csr("spiflash")
# Add ROM linker region
self.add_memory_region("rom",
self.mem_map["spiflash"] + flash_offset,
spiflash_size - flash_offset,
type="cached+linker")
# In debug mode, add a UART bridge. This takes over from the normal UART bridge,
# however you can use the "crossover" UART to communicate with this over the bridge.
if debug:
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), sys_clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu.debug_bus, 0x100)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
def __init__(self,
board,
revision,
with_ethernet=False,
with_etherbone=False,
sys_clk_freq=60e6,
**kwargs):
SoCCore.mem_map = {
"rom": 0x00000000,
"sram": 0x10000000,
"spiflash": 0x20000000,
"main_ram": 0x40000000,
"csr": 0x82000000,
}
board = board.lower()
assert board in ["5a-75e"]
if board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
# platform.add_extension(_serial)
if with_etherbone:
sys_clk_freq = int(125e6)
# SoCCore -----------------------------------------------------------
SoCCore.__init__(
self,
platform,
cpu_type="vexriscv",
# cpu_variant="lite+debug",
# cpu_variant="lite",
cpu_variant="linux",
csr_data_width=8,
# csr_data_width=32,
ident="LiTex Johnny RiscV",
# max_sdram_size=0x400000,
ident_version=True,
# cpu_reset_address=0x0,
# integrated_rom_size=0x8000,
# integrated_main_ram_size=0x4000)
# integrated_main_ram_size=0x0,
clk_freq=sys_clk_freq,
**kwargs)
# CRG ---------------------------------------------------------------
with_rst = kwargs["uart_name"] not in ["serial", "bridge"]
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_usb_pll=with_usb_pll,
with_rst=with_rst)
# SDR SDRAM ---------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram(
"sdram",
phy=self.sdrphy,
module=M12L16161A(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
# l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_size=kwargs.get("l2_size", 0x8000),
# 0x8000 = 32kiB, 32KiB * 128 = 4096KiB
l2_cache_min_data_width=kwargs.get("min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet / Etherbone ----------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Wishbone-UART bridge ----------------------------------------------
# self.submodules.serial_bridge = UARTWishboneBridge(
# platform.request("serial", 1),
# sys_clk_freq)
# self.add_wb_master(self.serial_bridge.wishbone)
# CPU DBG ----------------------------------------------------------
# self.register_mem(
# "vexriscv_lite_debug",
# 0xf00f0000,
# self.cpu.debug_bus,
# 0x10)
# LEDs -------------------------------------------------------------
user_leds = Cat(*[platform.request("user_led", i) for i in range(2)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(60e6),
with_ethernet=False,
with_etherbone=False,
with_spiflash=False,
ip_address=None,
mac_address=None,
**kwargs):
platform = colorlight_5a_75e.Platform()
platform.add_extension(ios)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteX LiteSPI SoC",
ident_version=True,
csr_data_width=32,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_rst=(kwargs["uart_name"] != "serial"))
# SDRAM ------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L16161A(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# SPIFlash ---------------------------------------------------------------------------------
if with_spiflash:
flash = W25Q32JV(Codes.READ_1_1_1)
self.submodules.spiflash_phy = LiteSPIPHY(
pads=platform.request("spiflash"),
flash=flash,
device=platform.device)
self.submodules.spiflash_mmap = LiteSPI(
phy=self.spiflash_phy,
clk_freq=sys_clk_freq,
mmap_endianness=self.cpu.endianness)
self.add_csr("spiflash_mmap")
self.add_csr("spiflash_phy")
spiflash_region = SoCRegion(origin=self.mem_map.get(
"spiflash", None),
size=flash.total_size,
cached=False)
self.bus.add_slave(name="spiflash",
slave=self.spiflash_mmap.bus,
region=spiflash_region)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address)