def main(ninputs,
noutputs,
input_isbits=True,
output_isbits=True,
has_clock=False):
assert 0 <= ninputs <= 8
assert 0 <= noutputs <= 8
print(m.mantle_target)
if m.mantle_target == 'ice40':
from loam.boards.icestick import IceStick
icestick = IceStick()
if has_clock:
icestick.Clock.on()
for i in range(ninputs):
icestick.J1[i].input().on()
for i in range(noutputs):
icestick.J3[i].output().on()
top = icestick.main()
if ninputs:
top.I = top.J1
if noutputs:
top.O = top.J3
elif m.mantle_target == 'spartan3' or m.mantle_target == 'spartan6':
from loam.boards.papilioone import PapilioOne
from loam.boards.papiliopro import PapilioPro
from loam.shields.megawing import MegaWing
Papilio = PapilioOne if m.mantle_target == 'spartan3' else PapilioPro
megawing = MegaWing(Papilio)
if has_clock:
megawing.Clock.on()
megawing.Switch.on(ninputs)
megawing.LED.on(noutputs)
top = megawing.main()
if ninputs:
top.I = top.SWITCH
if noutputs:
top.O = top.LED
else:
raise ValueError(m.mantle_target)
if ninputs == 1 and input_isbits:
top.I = m.bits([top.I])
if noutputs == 1 and output_isbits:
top.O = m.bits([top.O])
return top
def test(circuit, func):
icestick = IceStick()
icestick.Clock.on()
icestick.DSR.on()
icestick.CTS.on()
icestick.D1.on()
icestick.D2.on()
icestick.D3.on()
icestick.D4.on()
icestick.D5.on()
main = icestick.main()
finished, error = generate_test(circuit, func)
wire(finished, main.D3)
wire(finished, main.D4)
wire(finished, main.DSR)
wire(error, main.D1)
wire(error, main.D2)
wire(Not()(error), main.D5)
wire(error, main.CTS)
EndCircuit()
return main
def makepicoicestick(prog, ADDRN, DATAN):
icestick = IceStick()
icestick.Clock.on()
for i in range(8):
icestick.J1[i].input().on()
for i in range(8):
icestick.J3[i].output().on()
main = icestick.main()
pico, romb = makepico(prog, [main.J1], [main.J3], ADDRN, DATAN)
return main
def makepicoicestick(prog, ADDRN, DATAN, debug=None):
icestick = IceStick()
icestick.Clock.on()
for i in range(8):
icestick.J1[i].input().on()
for i in range(8):
icestick.J3[i].output().on()
main = icestick.main()
pico, romb = makepico(prog, main.J1, main.J3, ADDRN, DATAN, debug)
return main
def to_fpga(rx):
icestick = IceStick()
icestick.Clock.on()
icestick.D1.on()
main = icestick.DefineMain()
rom = string_to_rom('x' * 16)
matcher = Matcher(rx)
m.wire(rom, matcher.char)
m.wire(matcher.match, main.D1)
m.EndDefine()
m.compile('regulair', main)
def binary(Test, width):
import magma as m
from loam.boards.icestick import IceStick
icestick = IceStick()
for i in range(2*width):
icestick.J1[i].input().on()
for i in range(width):
icestick.J3[i].output().on()
top = icestick.main()
if width == 1:
top.J3 = [top.J3]
test = Test()
m.wire( test(top.J1[0:width], top.J1[width:2*width], 0), top.J3 )
m.EndCircuit()
return top
def test_counter():
icestick = IceStick()
icestick.Clock.on()
icestick.D1.on()
icestick.D2.on()
icestick.D3.on()
main = icestick.main()
count = Counter(2)
wire(count.O[0], main.D1)
wire(count.O[1], main.D2)
wire(count.COUT, main.D3)
simulator = PythonSimulator(main)
scope = Scope()
for i in range(2):
for i in range(4):
for j in range(2):
simulator.step()
simulator.evaluate()
assert bit_list_to_int(simulator.get_value(count.O, scope)) == i
assert int(simulator.get_value(main.D3, scope)) == 1
def test_lut4():
icestick = IceStick()
icestick.Clock.on()
icestick.J1[0].rename('I0').input().on()
icestick.J1[1].rename('I1').input().on()
icestick.J1[2].rename('I2').input().on()
icestick.J1[3].rename('I3').input().on()
icestick.J3[0].rename('D0').output().on()
main = icestick.main()
lut = SB_LUT4(LUT_INIT="16'h8000")
wire(main.I0, lut.I0)
wire(main.I1, lut.I1)
wire(main.I2, lut.I2)
wire(main.I3, lut.I3)
wire(lut.O, main.D0)
simulator = PythonSimulator(main)
scope = Scope()
simulator.set_value(main.I0, scope, False)
simulator.set_value(main.I1, scope, False)
simulator.set_value(main.I2, scope, False)
simulator.set_value(main.I3, scope, False)
for j in range(2):
simulator.step()
simulator.evaluate()
assert simulator.get_value(main.D0, scope) == False
simulator.set_value(main.I0, scope, True)
simulator.set_value(main.I1, scope, True)
simulator.set_value(main.I2, scope, True)
simulator.set_value(main.I3, scope, True)
for j in range(2):
simulator.step()
simulator.evaluate()
assert simulator.get_value(main.D0, scope) == True
from magma import array, wire, compile, EndCircuit
from loam.boards.icestick import IceStick
from mantle.lattice.ice40.RAMB import RAMB
icestick = IceStick()
icestick.Clock.on()
icestick.J1[0].rename('I0').input().on()
icestick.J1[1].rename('I1').input().on()
icestick.J1[2].rename('I2').input().on()
icestick.J1[3].rename('I3').input().on()
icestick.J1[4].rename('I4').input().on()
icestick.J1[5].rename('I5').input().on()
icestick.J1[6].rename('I6').input().on()
icestick.J3[0].rename('D0').output().on()
icestick.J3[1].rename('D1').output().on()
main = icestick.main()
WDATA = array([main.I0, main.I1])
WADDR = array([main.I2, main.I3, 0, 0, 0, 0, 0, 0, 0, 0, 0])
RADDR = array([main.I4, main.I5, 0, 0, 0, 0, 0, 0, 0, 0, 0])
WE = main.I6
O = array([main.D0, main.D1])
N = 2
M = 4096 // N
rom = M * [0]
for i in range(M):
rom[i] = i & 0x3
ramb = RAMB(M, N, rom)
#print(ramb.interface)
def test_icestick():
icestick = IceStick()
assert icestick
