def treatRam(Reg):
Access = getPrm(Reg, 'access', 'rw')
Wid = getPrm(Reg, 'width', 32)
Dep = getPrm(Reg, 'depth', 32)
Name = getPrm(Reg, 'names', ['err'])[0]
Line = ' ,input [%d:0] %s_rdata' % (Wid - 1, Name)
LINES[0].append(Line)
Line = ' ,output [%d:0] %s_addr' % (logs.neededBits(Dep - 1), Name)
LINES[0].append(Line)
Line = ' ,output %s_rd_pulse' % (Name)
LINES[0].append(Line)
Line = ' ,output %s_wr_pulse' % (Name)
LINES[0].append(Line)
Line = 'assign %s_addr = (mpaddr - \'h%x)>>2;' % (Name, Reg.Addr)
LINES[4].append(Line)
Str = string.replace(RAM_ROPULSE_RANGE, 'REG', Name)
Str = string.replace(Str, 'LADDR', hex(Reg.Addr)[2:])
Str = string.replace(Str, 'HADDR', hex(Reg.HADDR)[2:])
LINES[4].append(Str)
Str = string.replace(RWPULSE_RANGE, 'REG', Name)
Str = string.replace(Str, 'LADDR', hex(Reg.Addr)[2:])
Str = string.replace(Str, 'HADDR', hex(Reg.HADDR)[2:])
LINES[4].append(Str)
Line = '%s_rd_data_valid ? %s_rdata :' % (Name, Name)
Db['chip'].RAMS += Line
Db['chip'].RAMS_WIRES += 'wire %s_rd_data_valid;' % Name
def bodyDump1(Db, File):
Base = getPrm(Db['chip'], 'base', 0)
X = logs.neededBits(Db['chip'].Addr - Base)
Mask = ((1 << X) - 1) & 0xfffc
Str = string.replace(STRING0, 'MASK', hex(Mask)[2:])
Str = string.replace(Str, 'BASE', hex(Base)[2:])
File.write('%s\n' % Str)
for Line in LINES[1]:
File.write('%s\n' % Line)
File.write(" 32'hx;\n")
Str = Db['chip'].RAMS_WIRES + '\n' + string.replace(
STRING1, 'RAMS', Db['chip'].RAMS)
RST = getPrm(Db['chip'], 'reset', 'async')
if RST == 'async':
Str = string.replace(Str, 'ASYNCRST', 'or negedge rst_n')
else:
Str = string.replace(Str, 'ASYNCRST', '')
File.write('%s\n' % Str)
for Line in LINES[2]:
File.write('%s\n' % Line)
File.write(' end else if (pwrite) begin\n')
for Line in LINES[3]:
File.write('%s\n' % Line)
File.write(' end\n')
File.write('end\n')
for Line in LINES[4]:
File.write('%s\n' % Line)
File.write('endmodule\n')
def dumpApb():
Module = Db['chip'].Params['names'][0]
Str = string.replace(HEADER, 'MODULE', Module)
File = open('%s.v' % Module, 'w')
File.write(Str)
Db['module'] = Module
for Reg in Db['regs']:
if Reg.Kind == 'reg':
treatReg(Reg)
elif Reg.Kind == 'array':
treatArray(Reg)
elif Reg.Kind == 'ram':
treatRam(Reg)
elif Reg.Kind == 'gap':
pass
else:
logs.log_error('wrong kind %s' % (Reg.Kind, Reg.Params.Names))
for Line in LINES[0]:
File.write('%s\n' % Line)
Base = getPrm(Db['chip'], 'base', 0)
X = logs.neededBits(Db['chip'].Addr - Base)
Mask = ((1 << X) - 1) & 0xfffc
Str = string.replace(STRING0, 'MASK', hex(Mask)[2:])
Str = string.replace(Str, 'BASE', hex(Base)[2:])
File.write('%s\n' % Str)
for Line in LINES[1]:
File.write('%s\n' % Line)
File.write(" 32'hx;\n")
Str = Db['chip'].RAMS_WIRES + '\n' + string.replace(
STRING1, 'RAMS', Db['chip'].RAMS)
RST = getPrm(Db['chip'], 'reset', 'async')
if RST == 'async':
Str = string.replace(Str, 'ASYNCRST', 'or negedge rst_n')
else:
Str = string.replace(Str, 'ASYNCRST', '')
File.write('%s\n' % Str)
for Line in LINES[2]:
File.write('%s\n' % Line)
File.write(' end else if (apb_write && penable) begin\n')
for Line in LINES[3]:
File.write('%s\n' % Line)
File.write(' end\n')
File.write('end\n')
for Line in LINES[4]:
File.write('%s\n' % Line)
File.write('endmodule\n')
File.close()
def treatArray(Reg):
Access = getPrm(Reg, 'access', 'rw')
Wid = getPrm(Reg, 'width', 32)
Reset = getPrm(Reg, 'reset', 0)
Default = getPrm(Reg, 'default', 0)
if (Reset == 0) and (Default != 0): Reset = Default
Dep = getPrm(Reg, 'depth', 32)
Name = getPrm(Reg, 'names', ['err'])[0]
if 'external' in Access:
Line = ' ,input [%d:0] [%d:0] %s' % (Dep - 1, Wid - 1, Name)
LINES[0].append(Line)
Line = ' ,output %s_rd_pulse' % (Name)
LINES[0].append(Line)
Line = ' ,output %s_wr_pulse' % (Name)
LINES[0].append(Line)
Line = ' ,output [%d:0] %s_addr' % (logs.neededBits(Dep - 1) - 1,
Name)
LINES[0].append(Line)
Str = ROPULSE_RANGE.replace('REG', Name)
Str = Str.replace('LADDR', hex(Reg.Addr)[2:])
Str = Str.replace('HADDR', hex(Reg.HADDR)[2:])
LINES[4].append(Str)
Str = RWPULSE_RANGE.replace('REG', Name)
Str = Str.replace('LADDR', hex(Reg.Addr)[2:])
Str = Str.replace('HADDR', hex(Reg.HADDR)[2:])
LINES[4].append(Str)
elif outAccess(Access):
Line = ' ,output reg [%d:0] [%d:0] %s' % (Dep - 1, Wid - 1, Name)
LINES[0].append(Line)
Ad = Reg.Addr
Line = ' %s <= %d\'h%x;' % (Name, Dep * Wid, Reset)
LINES[2].append(Line)
Ad = Reg.Addr
for Ind in range(Dep):
Line = ' if (mpaddr == \'h%x) %s[%d] <= (%s[%d] & ~mask) | (wdata & mask);' % (
Ad, Name, Ind, Name, Ind)
LINES[3].append(Line)
Ad += simpleAdvanceAddr(Reg)
elif ('ro' in Access):
Line = ' ,input [%d:0] [%d:0] %s' % (Dep - 1, Wid - 1, Name)
LINES[0].append(Line)
Ad = Reg.Addr
busWid = Db['chip'].Params['width']
for Ind in range(Dep):
Line = ' (mpaddr == \'h%x) ? %s :' % (
Ad, expandBits(Name + '[%d]' % Ind, Wid, busWid))
Ad += simpleAdvanceAddr(Reg)
LINES[1].append(Line)
return
def apbHead():
Str = APBHead.replace('MODULE', Db['module'])
missParam(Db['chip'].Params, 'width', 32)
missParam(Db['chip'].Params, 'addrwid', 32)
Buswid = Db['chip'].Params['width']
Addwid = Db['chip'].Params['addrwid']
if Buswid == 32:
Wstrb = 4
else:
Wstrb = logs.neededBits(int(Buswid / 8))
Str = Str.replace('BUSWID', str(Buswid))
Str = Str.replace('ADDWID', str(Addwid))
Str = Str.replace('WSTRB', str(Wstrb))
Db['fout'].write(Str)
if 'external' in Db['chip'].Params:
Db['fout'].write(' ,output [%s:0] last_wdata\n' % (Buswid - 1))
def treatArray(Reg):
Access = getPrm(Reg, 'access', 'rw')
Wid = getPrm(Reg, 'width', 32)
Dep = getPrm(Reg, 'depth', 32)
Name = getPrm(Reg, 'names', ['err'])[0]
if 'external' in Access:
Line = ' ,input [%d:0] [%d:0] %s' % (Dep - 1, Wid - 1, Name)
LINES[0].append(Line)
Line = ' ,output %s_rd_pulse' % (Name)
LINES[0].append(Line)
Line = ' ,output %s_wr_pulse' % (Name)
LINES[0].append(Line)
Line = ' ,output [%d:0] %s_addr' % (logs.neededBits(Dep) - 1, Name)
LINES[0].append(Line)
Str = string.replace(ROPULSE_RANGE, 'REG', Name)
Str = string.replace(Str, 'LADDR', hex(Reg.Addr)[2:])
Str = string.replace(Str, 'HADDR', hex(Reg.HADDR)[2:])
LINES[4].append(Str)
Str = string.replace(RWPULSE_RANGE, 'REG', Name)
Str = string.replace(Str, 'LADDR', hex(Reg.Addr)[2:])
Str = string.replace(Str, 'HADDR', hex(Reg.HADDR)[2:])
LINES[4].append(Str)
elif ('wr' in Access) or ('rw' in Access):
Line = ' ,output reg [%d:0] [%d:0] %s' % (Dep - 1, Wid - 1, Name)
LINES[0].append(Line)
Ad = Reg.Addr
for Ind in range(Dep):
Line = ' (mpaddr == \'h%x) ? %s :' % (
Ad, expandBits(Name + '[%d]' % Ind, Wid, 32))
Ad += 4
LINES[1].append(Line)
Line = ' %s <= %d\'h%x;' % (Name, Wid, Reset)
LINES[2].append(Line)
elif ('ro' in Access):
Line = ' ,input [%d:0] [%d:0] %s' % (Dep - 1, Wid - 1, Name)
LINES[0].append(Line)
Ad = Reg.Addr
for Ind in range(Dep):
Line = ' (mpaddr == \'h%x) ? %s :' % (
Ad, expandBits(Name + '[%d]' % Ind, Wid, 32))
Ad += 4
LINES[1].append(Line)
return
def bodyDump1(Db, File):
Base = getPrm(Db['chip'], 'base', 0)
X = logs.neededBits(Db['chip'].Addr - Base)
Buswid = Db['chip'].Params['width']
Addwid = Db['chip'].Params['addrwid']
if Buswid == 128:
Mask = ((1 << Addwid) - 1) & 0xffffffe0
elif Buswid == 64:
Mask = ((1 << Addwid) - 1) & 0xfffffff8
elif Buswid == 32:
Mask = ((1 << Addwid) - 1) & 0xfffffffc
elif Buswid == 16:
Mask = ((1 << Addwid) - 1) & 0xfffffffe
elif Buswid == 8:
Mask = ((1 << Addwid) - 1) & 0xffffffff
if Buswid == 128: Wstrb = 16
elif Buswid == 64: Wstrb = 8
elif Buswid == 32: Wstrb = 4
elif Buswid == 16: Wstrb = 2
elif Buswid == 8: Wstrb = 1
else:
logs.log_error('#%d: BUSWIDTH is %d , allowed values are 32,64,128' %
(Reg.Lnum, Buswid))
Wstrb = 4
Buswid = 32
File.write(');\n')
for Line in LINES['split'] + LINES['split2']:
File.write('%s\n' % Line)
Str = 'wire [BUSWID-1:0] wdata = pwdata;\n'.replace('BUSWID', str(Buswid))
File.write(Str)
for Line in LINES[10]:
File.write('%s\n' % Line)
# Haddr = Db['chip'].HADDR
Str = STRING0.replace('MASK', hex(Mask)[2:])
Str = Str.replace('BASE', hex(Base)[2:])
Str = Str.replace('BUSWID', str(Buswid))
Str = Str.replace('ADDWID', str(Addwid))
Str = Str.replace('WSTRB', str(Wstrb))
File.write('%s\n' % Str)
for Line in LINES[1]:
File.write('%s\n' % Line)
Default = getPrm(Db['chip'], 'empty', "0xdeaddead")
if (type(Default) is int):
Default = hex(Default)[2:]
elif (type(Default) is str):
try:
Default = eval(Default)
except:
logs.log_error(
'#empty of chip (default value for cases) is not a legal integer "%s"'
% (Default))
Default = '0; // BAD DEFAULT %s' % Default
File.write(" %d'h%s;\n" % (Buswid, Default))
Str = STRING1.replace('RAMS', Db['chip'].RAMS)
Str = Str.replace('BUSWID', str(Buswid))
Str = Str.replace('ADDWID', str(Addwid))
Str = Str.replace('WSTRB', str(Wstrb))
if Buswid == 128:
Str = Str.replace('PSTRB', PSTRB16)
if Buswid == 64:
Str = Str.replace('PSTRB', PSTRB8)
elif Buswid == 32:
Str = Str.replace('PSTRB', PSTRB4)
elif Buswid == 16:
Str = Str.replace('PSTRB', PSTRB2)
elif Buswid == 8:
Str = Str.replace('PSTRB', PSTRB1)
Str = Db['chip'].RAMS_WIRES + '\n' + Str
RST = getPrm(Db['chip'], 'reset', 'async')
if RST == 'async':
Str = Str.replace('ASYNCRST', 'or negedge presetn')
else:
Str = Str.replace('ASYNCRST', '')
File.write('%s\n' % Str)
for Line in LINES[2]:
File.write('%s\n' % Line)
File.write(' end else if (pwrite) begin\n')
for Line in LINES[3]:
Reg = Line.split()[4]
if Reg in Db['splitsw']:
Obj = Db['splits'][Reg]
Map = Db['splitsw'][Reg]
Map.reverse()
Bin = ''.join(Map)
Int = int(Bin, 2)
MASK = "%d'h%x" % (Obj.Params['width'], Int)
Line = Line.replace('<= ', '<= %s & (' % MASK)
Line = Line.replace(';', ');')
File.write('%s\n' % Line)
File.write(' end\n')
File.write('end\n')
for Line in LINES[4]:
File.write('%s\n' % Line)
File.write('endmodule\n')
def treatRam(Reg):
Access = getPrm(Reg, 'access', 'rw')
Wid = getPrm(Reg, 'width', 32)
Dep = getPrm(Reg, 'depth', 32)
Name = getPrm(Reg, 'names', ['err'])[0]
Line = ' ,input [%d:0] %s_rdata' % (Wid - 1, Name)
LINES[0].append(Line)
Line = ' ,output [%d:0] %s_wdata' % (Wid - 1, Name)
LINES[0].append(Line)
Line = ' ,output [%d:0] %s_addr' % (logs.neededBits(Dep - 1) - 1, Name)
LINES[0].append(Line)
Line = ' ,output %s_rd_pulse' % (Name)
LINES[0].append(Line)
Line = ' ,output %s_wr_pulse' % (Name)
LINES[0].append(Line)
BusWidth = Db['chip'].Params['width']
BusBytes = int(BusWidth / 8)
if BusBytes == 8: AdShift = 3
elif BusBytes == 4: AdShift = 2
Line = 'wire [2:0] ExtraBytes%s = pstrb[0] ? 0 : pstrb[1] ? 1 : pstrb[2] ? 2 : pstrb[3] ? 3 ' % (
Name)
if (BusBytes == 8):
Line += ': pstrb[4] ? 4 : pstrb[5] ? 5 : pstrb[6] ? 6 : 7;'
else:
Line += ': 0;'
LINES[4].append(Line)
if (Wid == 8): Adjust = 0
elif (Wid == 16): Adjust = 1
elif (Wid == 32): Adjust = 2
elif (Wid == 64): Adjust = 3
# Line = 'wire [2:0] Extra%s = ExtraBytes%s>>%s;'%(Name,Name,Adjust)
# LINES[4].append(Line)
if (BusWidth == 64):
Line = 'assign %s_addr = ((mpaddr - \'h%x)>>%s);' % (Name, Reg.Addr, 3)
elif (BusWidth == 32):
Line = 'assign %s_addr = ((mpaddr - \'h%x)>>%s);' % (Name, Reg.Addr, 2)
LINES[4].append(Line)
if BusWidth == Wid:
Line = 'assign %s_wdata = wdata;' % (Name)
elif (BusWidth > Wid):
Line = 'assign %s_wdata = wdata[%d:0];' % (Name, Wid - 1)
LINES[4].append(Line)
if 'ready' in Reg.Params:
Line = ' ,input %s_ready' % (Name)
LINES[0].append(Line)
LINES[9].append(('ram', Name))
Str = RAM_ROPULSE_RANGE.replace('REG', Name)
Str = Str.replace('LADDR', hex(Reg.Addr)[2:])
Str = Str.replace('HADDR', hex(Reg.HADDR)[2:])
LINES[4].append(Str)
Str = RAM_RWPULSE_RANGE.replace('REG', Name)
Str = Str.replace('LADDR', hex(Reg.Addr)[2:])
Str = Str.replace('HADDR', hex(Reg.HADDR)[2:])
LINES[4].append(Str)
if (BusWidth == Wid):
Line = ' %s_rd_data_valid ? %s_rdata :\n' % (Name, Name)
elif (BusWidth == (2 * Wid)):
Line = ' %s_rd_data_valid ? {%s_rdata,%s_rdata} :\n' % (Name, Name,
Name)
elif (BusWidth == (4 * Wid)):
Line = ' %s_rd_data_valid ? {%s_rdata,%s_rdata,%s_rdata,%s_rdata} :\n' % (
Name, Name, Name, Name, Name)
elif (BusWidth == (8 * Wid)):
Line = ' %s_rd_data_valid ? {%s_rdata,%s_rdata,%s_rdata,%s_rdata,%s_rdata,%s_rdata,%s_rdata,%s_rdata} :\n' % (
Name, Name, Name, Name, Name, Name, Name, Name, Name)
else:
Line = ' %s_rd_data_valid ? %s_rdata :\n' % (Name, Name)
Db['chip'].RAMS += Line
Db['chip'].RAMS_WIRES += 'wire %s_rd_data_valid;' % Name