def addL1L2L3(self, args, L2Cache, L3Cache):
# Comm between L1-L2
self.l2bus = SystemXBar()
# Comm betweem L2-L3
self.l3bus = SystemXBar()
# Comm between L3-MainMem
self.membus = SystemXBar()
self.l2cache = L2Cache
self.l3cache = L3Cache
self.l2cache.cpu_side = self.l2bus.master
self.l2cache.mem_side = self.l3bus.slave
self.l3cache.cpu_side = self.l3bus.master
self.l3cache.mem_side = self.membus.slave
for core in self.cpu:
core.icache = BasicL1ICache(args)
core.dcache = BasicL1DCache(args)
core.icache.cpu_side = core.icache_port
core.icache.mem_side = self.l2bus.slave
core.dcache.cpu_side = core.dcache_port
core.dcache.mem_side = self.l2bus.slave
def _get_default_membus() -> SystemXBar:
"""
A method used to obtain the default memory bus of 64 bit in width for
the PrivateL1CacheHierarchy.
:returns: The default memory bus for the PrivateL1PrivateL2
CacheHierarchy.
"""
membus = SystemXBar(width=64)
membus.badaddr_responder = BadAddr()
membus.default = membus.badaddr_responder.pio
return membus