def sumsize(type): if issubclass(type, Sum): if hasattr(type, 'tags'): s = clog2(max([val for val in type.tags.values()])+1) else: s = clog2(len(type.fields)) return s
def test_decoded_output(NO): if NO == 1: LOGNO = clog2(NO + 1) + 1 else: LOGNO = clog2(NO) + 1 _, _, _, dout = assemble(main, LOGN, LOGNI, LOGNO) output = DefineDecodedOutput(dout, LOGN, LOGNO, NO) assert len(output.pc) == LOGN assert len(output.O) == NO
def test_input(NI): LOGNI = clog2(NI) _, _, din, _ = assemble(main, LOGN, LOGNI, LOGNO) input = DefineInput(din, LOGN, LOGNI) assert len(input.pc) == LOGN assert len(input.I) == NI print(input)
def configure(n, ni, no, output): logn = clog2(n) assert logn <= MAXLOGN logni = clog2(ni) assert logni <= MAXLOGNI if output == 'decoded': if no == 1: no = 2 logno = clog2(no) + 1 # 1 extra bit for output value else: logno = no assert logno <= MAXLOGNO return logn, logni, logno
def shift(Test, width): logwidth = clog2(width) print(width, logwidth) top = main(width + logwidth, width) test = Test(width) print(type(test)) m.wire(test(top.I[0:width], top.I[width:width + logwidth]), top.O) m.EndCircuit() return top
def size(type): s = 0 if issubclass(type, AbstractBit): s = 1 elif issubclass(type, AbstractBitVector): s = type.size elif issubclass(type, Enum): return clog2(len(list(type.enumerate()))) elif issubclass(type, Product): s = sum([size(getattr(type,key)) for key in type.field_dict]) elif issubclass(type, Sum): s = max([size(f) for f in type.fields]) + sumsize(type) return s
def test_decoded_clock(has_ce, has_reset): NO = 2 LOGNO = clog2(NO) + 1 _, _, _, dout = assemble(main, LOGN, LOGNI, LOGNO) output = DefineDecodedOutput(dout, LOGN, LOGNO, NO, has_ce=has_ce, has_reset=has_reset) assert len(output.pc) == LOGN assert len(output.O) == NO assert not has_ce or hasattr(output, 'CE') assert not has_reset or hasattr(output, 'RESET')
def DefineRAM(height, width): addr_width = clog2(height) TADDR = Bits[ addr_width ] TDATA = Bits[ width ] class _RAM(Circuit): name = f'RAM{height}x{width}' IO = ['RADDR', In(TADDR), 'RDATA', Out(TDATA), 'WADDR', In(TADDR), 'WDATA', In(TDATA), 'WE', In(Bit), 'CLK', In(Clock) ] @classmethod def definition(io): regs = REGs(height, width, has_ce=True) writeport(addr_width, width, regs, io.WADDR, io.WDATA, io.WE) wire( readport(addr_width, width, regs, io.RADDR), io.RDATA ) return _RAM
def LUT(init, N=None, **kwargs): """ n-bit LUT I0 : In(Bit), I1 : In(Bit), ..., In : In(Bit), O : Out(Bit) """ if isinstance(init, FunctionType): init = fun2seq(init, 1 << N) if isinstance(init, Sequence): if N is not None: if 2**N < len(init): raise ValueError("init is too large for N={}".format(N)) else: N = clog2(len(init)) init = seq2int(init) else: if N is None: raise ValueError("N requires for not sequence init") return DefineLUT(init, N)()
import magma magma.set_mantle_target('spartan6') from magma.bitutils import clog2 from bit1.asm import assemble, disassemble N = 32 LOGN = clog2(N) NI = 2 LOGNI = clog2(NI) NO = 2 LOGNO = clog2(NO) + 1 def prog(): from bit1.isa import set, clr from bit1.isa import mov, not_, and_, or_, xor from bit1.isa import nop, delay from bit1.isa import jump from bit1.isa import if0, if1, ifelse from bit1.isa import skip, skipif0, skipif1 from bit1.isa import halt set( O0 ) clr( O0 ) mov( I0, O0 ) not_( I0, O0 ) and_( I0, I1, O0 ) or_( I0, I1, O0 ) xor( I0, I1, O0 ) delay(1)
def asr(I0, I1, **kwargs): width = get_length(I0) shift = get_length(I1) if shift != clog2(width): raise ValueError("ASR shift should be equal to the clog2 of width") return ASR(width, **kwargs)(I0, I1)
import pytest from magma.bitutils import clog2 from bit1.asm import assemble from bit1 import DefineInput N = 32 LOGN = clog2(N) NO = 2 LOGNO = clog2(NO) + 1 def main(): from bit1.isa import and_, jump, I0, I1, O0 and_(I0, I1, O0) jump(0) @pytest.mark.parametrize("NI", [2, 4, 8, 16]) def test_input(NI): LOGNI = clog2(NI) _, _, din, _ = assemble(main, LOGN, LOGNI, LOGNO) input = DefineInput(din, LOGN, LOGNI) assert len(input.pc) == LOGN assert len(input.I) == NI print(input)
import pytest from magma.bitutils import clog2 from bit1.asm import assemble from bit1 import DefineDecodedOutput, DefineOutput N = 32 LOGN = clog2(N) NI = 2 LOGNI = clog2(NI) def main(): from bit1.isa import and_, jump, I0, I1, O0 and_(I0, I1, O0) jump(0) @pytest.mark.parametrize("NO", [1, 2, 3, 4, 5, 6, 7, 8, 16]) def test_decoded_output(NO): if NO == 1: LOGNO = clog2(NO + 1) + 1 else: LOGNO = clog2(NO) + 1 _, _, _, dout = assemble(main, LOGN, LOGNI, LOGNO) output = DefineDecodedOutput(dout, LOGN, LOGNO, NO) assert len(output.pc) == LOGN assert len(output.O) == NO #print(output)
import magma as m from magma.bitutils import clog2 from mantle.util.compressor import PopCount from loam.boards.icestick import IceStick N = 128 LOGN = min(clog2(N) + 1, 8) icestick = IceStick() for i in range(8): icestick.J1[i].input().on() for i in range(LOGN): icestick.J3[i].output().on() main = icestick.main() pop = PopCount(N) for i in range(len(pop.I)): pop.I[i] <= (main.J1[i] if i < 8 else 0) main.J3 <= pop.O[0:LOGN] m.EndCircuit()
def test_shift(op, width): from magma.bitutils import clog2 total = width + clog2(width) if total < 8: Test = getattr(mantle, op) com(f'{op}{width}', shift(Test, width))