def inst(o, i=None, next_pc0=None, next_pc1=None, **kwargs):
global _pc, _mem
#if _pass == 1:
# print(_pc, 'inst',o,i,next_pc0,next_pc1)
# print('mem[0]=',_mem[0])
if decoded:
if o == None:
oaddr = RNULL
odata = 0
else:
oaddr = o[0]
odata = o[1]
assert 0 <= oaddr < (1 << LOGNO - 1)
assert odata == 0 or odata == 1
o = int2seq(oaddr | odata << LOGNO - 1, LOGNO)
else:
assert o != None
jump = kwargs.get('jump', None)
skip = kwargs.get('skip', None)
if i is None:
i = 0
next_pc0 = None
next_pc1 = None
assert 0 <= i < NI
i = int2seq(i, LOGNI) if LOGNI > 0 else [0]
if next_pc0 is None:
if jump is not None: next_pc0 = jump
elif skip is not None: next_pc0 = (_pc + skip + 1) % N
else: next_pc0 = (_pc + 1) % N
if next_pc1 is None:
if jump is not None: next_pc1 = jump
elif skip is not None: next_pc1 = (_pc + skip + 1) % N
else: next_pc1 = (_pc + 1) % N
assert 0 <= next_pc0 < N
assert 0 <= next_pc1 < N
#if _pass == 1:
# print('fullinst',o,i,next_pc0,next_pc1)
next_pc0 = int2seq(next_pc0, LOGN)
next_pc1 = int2seq(next_pc1, LOGN)
assert _pc < N
_mem[_pc] = [o, i, next_pc0, next_pc1]
setpc((_pc + 1) % N)
def SRL16(init=0, has_shiftout=False, has_ce=False):
"""
Create a 16-bit shift register using a LUT
[I, A[4]] -> O
"""
if isinstance(init, IntegerTypes):
init = int2seq(init, 16)
if has_shiftout:
srl16 = SRLC16E(INIT=lutinit(init,16))
else:
srl16 = SRL16E(INIT=lutinit(init,16))
args = ["A", bits([srl16.A0, srl16.A1, srl16.A2, srl16.A3]),
"I", srl16.D,
"O", srl16.Q]
if has_ce:
args += ["CE", srl16.CE]
else:
wire(1,srl16.CE)
if has_shiftout:
args += ["SHIFTOUT", srl16.Q15]
args += ["CLK", srl16.CLK]
return AnonymousCircuit(args)
def SRL32(init=0, has_shiftout=False, has_ce=False):
"""
Configure a Slice as a 32-bit shift register
[I, A[5]] -> O
@note: SRL32's can be chained together using SHIFTOUT and SHIFTIN.
In that case, an SRL32 does not generate any output.
"""
if isinstance(init, IntegerTypes):
init = int2seq(init, 32)
A = In(Bits(5))()
srl0 = SRL16(init[ 0:16], has_shiftout=True, has_ce=has_ce)
srl1 = SRL16(init[16:32], has_shiftout=True, has_ce=has_ce)
srls = [srl0, srl1]
srl = braid( srls, forkargs=['A', 'CE', 'CLK'], foldargs={"I":"SHIFTOUT"} )
wire( A[0:4], srl.A )
mux = MUXF5()
mux(srl.O[0], srl.O[1], A[4])
args = ["A", A, "I", srl.I, "O", mux.O]
if has_ce:
args += ['CE', srl.CE]
args += ['CLK', srl.CLK]
return AnonymousCircuit(args)
def SRL32(init=0, has_shiftout=False, has_ce=False):
"""
Configure a Slice as a 32-bit shift register
[I, A[5]] -> O
@note: SRL32's can be chained together using SHIFTOUT and SHIFTIN.
In that case, an SRL32 does not generate any output.
"""
if isinstance(init, IntegerTypes):
init = int2seq(init, 32)
srl32 = SRL32E(INIT=lutinit(init,64))
args = ["A", srl32.A,
"O", srl32.Q,
"I", srl32.D]
if has_ce:
args += ["CE", srl32.CE]
else:
wire(1,srl32.CE)
if has_shiftout:
args += ["SHIFTOUT", srl32.Q31]
args += ["CLK", srl32.CLK]
return AnonymousCircuit(args)
def LUT6x2(rom5, rom6):
if isinstance(rom5, types.FunctionType):
rom5 = fun2seq(rom5, 32)
if isinstance(rom5, IntegerTypes):
rom5 = int2seq(rom5, 32)
if isinstance(rom6, types.FunctionType):
rom6 = fun2seq(rom6, 32)
if isinstance(rom6, IntegerTypes):
rom6 = int2seq(rom6, 32)
lut = _LUT6x2(INIT=lutinit(rom5 + rom6, 1 << 6))
return AnonymousCircuit("I0", lut.I0, "I1", lut.I1, "I2", lut.I2, "I3",
lut.I3, "I4", lut.I4, "I5", lut.I5, "O5", lut.O5,
"O6", lut.O6)
def interleave16(data, width):
n = len(data)
bits = [int2seq(data[i], width) for i in range(n)]
#print(n, bits)
data = [ [ [bits[i+j][w] for j in range(16)] for w in range(width)] \
for i in range(0,n,16) ]
#print(len(data), data)
return data
def FFs(n, init=0, has_ce=False, has_reset=False, has_set=False):
if isinstance(init, IntegerTypes):
init = int2seq(init, n)
def f(y):
return FF(init[y], has_ce=has_ce, has_reset=has_reset, has_set=has_set)
return col(f, n)
def lfsr_sim():
regs = int2seq(init, N)
while True:
O = seq2int(regs)
print(O)
yield O
I = 0
for tap in taps:
I ^= regs[tap - 1]
regs = [I] + regs[:-1]
def LUT5(rom, **kwargs):
if isinstance(rom, IntegerTypes):
rom = int2seq(rom, 32)
I0, I1, I2, I3, I4 = In(Bit)(), In(Bit)(), In(Bit)(), In(Bit)(), In(Bit)()
lut = fork(LUT4(rom[0:16]), LUT4(rom[16:32]))
lut(I0, I1, I2, I3)
mux = Mux2()
mux(lut.O[0], lut.O[1], I4)
return AnonymousCircuit("I0", I0, "I1", I1, "I2", I2, "I3", I3, "I4", I4,
"O", mux.O)
def LUT8(rom, **kwargs):
if isinstance(rom, IntegerTypes):
rom = int2seq(rom, 256)
I0, I1, I2, I3, I4, I5, I6, I7 = In(Bit)(), In(Bit)(), In(Bit)(), In(
Bit)(), In(Bit)(), In(Bit)(), In(Bit)(), In(Bit)()
lut = fork(LUT7(rom[0:128]), LUT7(rom[128:256]))
mux = Mux2()
lut(I0, I1, I2, I3, I4, I5, I6)
mux(lut.O[0], lut.O[1], I7)
return AnonymousCircuit("I0", I0, "I1", I1, "I2", I2, "I3", I3, "I4", I4,
"I5", I5, "I6", I6, "I7", I7, "O", mux.O)
def LUT6(rom, **kwargs):
if isinstance(rom, IntegerTypes):
rom = int2seq(rom, 64)
I0, I1, I2, I3, I4, I5 = In(Bit)(), In(Bit)(), In(Bit)(), In(Bit)(), In(
Bit)(), In(Bit)()
lut = fork(LUT5(rom[0:32]), LUT5(rom[32:64]))
mux = Mux2()
lut(I0, I1, I2, I3, I4)
mux(lut.O[0], lut.O[1], I5)
return AnonymousCircuit("I0", I0, "I1", I1, "I2", I2, "I3", I3, "I4", I4,
"I5", I5, "O", mux.O)
def LUT7(rom, **kwargs):
if isinstance(rom, IntegerTypes):
rom = int2seq(rom, 128)
I = In(Bits(7))()
# need to convert rom to a sequence
lut0 = LUT6(rom[0:64])
lut1 = LUT6(rom[64:128])
lut = fork(lut0, lut1)
lut(I[0], I[1], I[2], I[3], I[4], I[5])
mux = MUXF7()
mux(lut.O[0], lut.O[1], I[6])
return AnonymousCircuit("I0", I[0], "I1", I[1], "I2", I[2], "I3", I[3],
"I4", I[4], "I5", I[5], "I6", I[6], "O", mux.O)
def FFs(n, init=0, has_ce=False, has_reset=False, has_async_reset=False):
if isinstance(init, IntegerTypes):
init = int2seq(init, n)
def f(y):
if mantle_target == "coreir":
return FF(init[y], has_ce=has_ce, has_reset=has_reset, has_async_reset=has_async_reset)
else:
if has_async_reset:
raise NotImplementedError()
return FF(init[y], has_ce=has_ce, has_reset=has_reset)
return col(f, n)
def LUT7(rom, **kwargs):
if isinstance(rom, IntegerTypes):
rom = int2seq(rom, 128)
I0, I1, I2, I3, I4, I5, I6 = In(Bit)(), In(Bit)(), In(Bit)(), In(Bit)(), In(Bit)(), In(Bit)(), In(Bit)()
lut = fork( LUT6(rom[ 0:64]), LUT6(rom[64:128]))
mux = MUXF7()
lut(I0, I1, I2, I3, I4, I5)
mux(lut.O[0], lut.O[1], I6)
return AnonymousCircuit("I0", I0,
"I1", I1,
"I2", I2,
"I3", I3,
"I4", I4,
"I5", I5,
"I6", I6,
"O", mux.O)
def atom_or_sseq_to_bits(atom: Union[int, bool, Tuple]) -> Tuple:
"""
This converts atoms or SSeqs of atoms to flat bits
:return:
"""
if type(atom) == int:
return builtins.tuple(int2seq(atom, int_width))
elif type(atom) == bool:
if atom == True:
return builtins.tuple([1])
else:
return builtins.tuple([0])
elif isinstance(atom, Iterable):
return builtins.tuple(ae_flatten([atom_or_sseq_to_bits(subatom) for subatom in atom]))
else:
raise NotImplementedError("Type {} not supported".format(str(type(atom))))
def LUT8(rom, **kwargs):
if isinstance(rom, IntegerTypes):
rom = int2seq(rom, 256)
I = Bits[ 8 ]()
# need to convert rom to a sequence
lut0 = LUT7(rom[ 0:128])
lut1 = LUT7(rom[128:256])
lut = fork(lut0, lut1)
lut(I[0], I[1], I[2], I[3], I[4], I[5], I[6])
mux = MUXF8()
mux(lut.O[0], lut.O[1], I[7])
return AnonymousCircuit("I0", I[0],
"I1", I[1],
"I2", I[2],
"I3", I[3],
"I4", I[4],
"I5", I[5],
"I6", I[6],
"I7", I[7],
"O", mux.O)
def simulate_lut4(self, value_store, state_store):
init = self.kwargs['INIT']
if isinstance(init, six.string_types):
a = init.split("'")
l = int(a[0])
p = a[1][0]
if p == 'h':
base = 16
else:
base = 10
i = int(a[1][1:], base)
init = lutinit(i, l)
if isinstance(init, int):
init = (init, 16)
lut = int2seq(init[0], init[1])
lut = [bool(i) for i in lut]
inputs = self.interface.inputs()
I = [value_store.get_value(inputs[x]) for x in range(0, 4)]
idx = seq2int(I)
val = lut[idx]
value_store.set_value(self.O, val)
def padded_int2seq(x):
return int2seq(x, n=bit_width)
def simulate(self, value_store, state_store):
in_ = value_store.get_value(getattr(self, "in"))
value_store.set_value(self.out,
[bool(i)
for i in int2seq(init, 2**N)][seq2int(in_)])
def set_value(ints):
f = lambda px: int2seq(px, bit_width)
bit_arrays = [[f(px) for px in row] for row in ints]
sim.set_value(LineBufferDef.I, bit_arrays, scope)
def test_lut(lut_code):
inst = asm.lut(lut_code)
for i in range(0, 8):
bit0, bit1, bit2 = int2seq(i, 3)
expected = (lut_code >> i)[0]
rtl_tester(inst, bit0=bit0, bit1=bit1, bit2=bit2, res_p=expected)
def definition(cls):
# first section creates the RAMs and LUTs that set values in them and the sorting network
shared_and_diff_subtypes = get_shared_and_diff_subtypes(
t_in, t_out)
t_in_diff = shared_and_diff_subtypes.diff_input
t_out_diff = shared_and_diff_subtypes.diff_output
graph = build_permutation_graph(ST_TSeq(2, 0, t_in_diff),
ST_TSeq(2, 0, t_out_diff))
banks_write_addr_per_input_lane = get_banks_addr_per_lane(
graph.input_nodes)
input_lane_write_addr_per_bank = get_lane_addr_per_banks(
graph.input_nodes)
output_lane_read_addr_per_bank = get_lane_addr_per_banks(
graph.output_nodes)
# each ram only needs to be large enough to handle the number of addresses assigned to it
# all rams receive the same number of writes
# but some of those writes don't happen as the data is invalid, so don't need storage for them
max_ram_addrs = [
max([bank_clock_data.addr for bank_clock_data in bank_data])
for bank_data in output_lane_read_addr_per_bank
]
# rams also handle parallelism from outer_shared type as this affects all banks the same
outer_shared_sseqs = remove_tseqs(
shared_and_diff_subtypes.shared_outer)
if outer_shared_sseqs == ST_Tombstone():
ram_element_type = shared_and_diff_subtypes.shared_inner
else:
ram_element_type = replace_tombstone(
outer_shared_sseqs, shared_and_diff_subtypes.shared_inner)
# can use wider rams rather than duplicate for outer_shared_sseqs because will
# transpose dimenions of input wires below to wire up as if outer, shared dimensions
# were on the inside
rams = [
DefineRAM_ST(ram_element_type, ram_max_addr + 1)()
for ram_max_addr in max_ram_addrs
]
rams_addr_widths = [ram.WADDR.N for ram in rams]
# for bank, the addresses to write to each clock
write_addr_for_bank_luts = []
for bank_idx in range(len(rams)):
ram_addr_width = rams_addr_widths[bank_idx]
num_addrs = len(input_lane_write_addr_per_bank[bank_idx])
#assert num_addrs == t_in_diff.time()
write_addrs = [
builtins.tuple(
int2seq(write_data_per_bank_per_clock.addr,
ram_addr_width))
for write_data_per_bank_per_clock in
input_lane_write_addr_per_bank[bank_idx]
]
write_addr_for_bank_luts.append(
DefineLUTAnyType(Array[ram_addr_width, Bit], num_addrs,
builtins.tuple(write_addrs))())
# for bank, whether to actually write this clock
write_valid_for_bank_luts = []
for bank_idx in range(len(rams)):
num_valids = len(input_lane_write_addr_per_bank[bank_idx])
#assert num_valids == t_in_diff.time()
valids = [
builtins.tuple([write_data_per_bank_per_clock.valid])
for write_data_per_bank_per_clock in
input_lane_write_addr_per_bank[bank_idx]
]
write_valid_for_bank_luts.append(
DefineLUTAnyType(Bit, num_valids,
builtins.tuple(valids))())
# for each input lane, the bank to write to each clock
write_bank_for_input_lane_luts = []
bank_idx_width = getRAMAddrWidth(len(rams))
for lane_idx in range(len(banks_write_addr_per_input_lane)):
num_bank_idxs = len(banks_write_addr_per_input_lane[lane_idx])
#assert num_bank_idxs == t_in_diff.time()
bank_idxs = [
builtins.tuple(
int2seq(write_data_per_lane_per_clock.bank,
bank_idx_width))
for write_data_per_lane_per_clock in
banks_write_addr_per_input_lane[lane_idx]
]
write_bank_for_input_lane_luts.append(
DefineLUTAnyType(Array[bank_idx_width, Bit], num_bank_idxs,
builtins.tuple(bank_idxs))())
# for each bank, the address to read from each clock
read_addr_for_bank_luts = []
for bank_idx in range(len(rams)):
ram_addr_width = rams_addr_widths[bank_idx]
num_addrs = len(output_lane_read_addr_per_bank[bank_idx])
#assert num_addrs == t_in_diff.time()
read_addrs = [
builtins.tuple(
int2seq(read_data_per_bank_per_clock.addr,
ram_addr_width))
for read_data_per_bank_per_clock in
output_lane_read_addr_per_bank[bank_idx]
]
read_addr_for_bank_luts.append(
DefineLUTAnyType(Array[ram_addr_width, Bit], num_addrs,
builtins.tuple(read_addrs))())
# for each bank, the lane to send each read to
output_lane_for_bank_luts = []
# number of lanes equals number of banks
# some the lanes are just always invalid, added so input lane width equals output lane width
lane_idx_width = getRAMAddrWidth(len(rams))
for bank_idx in range(len(rams)):
num_lane_idxs = len(output_lane_read_addr_per_bank[bank_idx])
#assert num_lane_idxs == t_in_diff.time()
lane_idxs = [
builtins.tuple(
int2seq(read_data_per_bank_per_clock.s,
lane_idx_width))
for read_data_per_bank_per_clock in
output_lane_read_addr_per_bank[bank_idx]
]
output_lane_for_bank_luts.append(
DefineLUTAnyType(Array[lane_idx_width, Bit], num_lane_idxs,
builtins.tuple(lane_idxs))())
# second part creates the counters that index into the LUTs
# elem_per counts time per element of the reshape
elem_per_reshape_counter = AESizedCounterModM(
ram_element_type.time(), has_ce=True)
end_cur_elem = Decode(ram_element_type.time() - 1,
elem_per_reshape_counter.O.N)(
elem_per_reshape_counter.O)
# reshape counts which element in the reshape
num_clocks = len(output_lane_read_addr_per_bank[0])
reshape_write_counter = AESizedCounterModM(num_clocks,
has_ce=True,
has_reset=has_reset)
reshape_read_counter = AESizedCounterModM(num_clocks,
has_ce=True,
has_reset=has_reset)
output_delay = (
get_output_latencies(graph)[0]) * ram_element_type.time()
# this is present so testing knows the delay
cls.output_delay = output_delay
reshape_read_delay_counter = DefineInitialDelayCounter(
output_delay, has_ce=True, has_reset=has_reset)()
# outer counter the repeats the reshape
#wire(reshape_write_counter.O, cls.reshape_write_counter)
enabled = DefineCoreirConst(1, 1)().O[0]
if has_valid:
enabled = cls.valid_up & enabled
wire(reshape_read_delay_counter.valid, cls.valid_down)
if has_ce:
enabled = bit(cls.CE) & enabled
wire(enabled, elem_per_reshape_counter.CE)
wire(enabled, reshape_read_delay_counter.CE)
wire(enabled & end_cur_elem, reshape_write_counter.CE)
wire(enabled & end_cur_elem & reshape_read_delay_counter.valid,
reshape_read_counter.CE)
if has_reset:
wire(cls.RESET, elem_per_reshape_counter.RESET)
wire(cls.RESET, reshape_read_delay_counter.RESET)
wire(cls.RESET, reshape_write_counter.RESET)
wire(cls.RESET, reshape_read_counter.RESET)
# wire read and write counters to all LUTs
for lut in write_bank_for_input_lane_luts:
wire(reshape_write_counter.O, lut.addr)
for lut in write_addr_for_bank_luts:
wire(reshape_write_counter.O, lut.addr)
for lut in write_valid_for_bank_luts:
wire(reshape_write_counter.O, lut.addr)
for lut in read_addr_for_bank_luts:
wire(reshape_read_counter.O, lut.addr)
for lut in output_lane_for_bank_luts:
wire(reshape_read_counter.O, lut.addr)
# third and final instance creation part creates the sorting networks that map lanes to banks
input_sorting_network_t = Tuple(
bank=Array[write_bank_for_input_lane_luts[0].data.N, Bit],
val=ram_element_type.magma_repr())
input_sorting_network = DefineBitonicSort(input_sorting_network_t,
len(rams),
lambda x: x.bank)()
output_sorting_network_t = Tuple(
lane=Array[output_lane_for_bank_luts[0].data.N, Bit],
val=ram_element_type.magma_repr())
output_sorting_network = DefineBitonicSort(
output_sorting_network_t, len(rams), lambda x: x.lane)()
# wire luts, sorting networks, inputs, and rams
# flatten all the sseq_layers to get flat magma type of inputs and outputs
# tseqs don't affect magma types
num_sseq_layers_inputs = num_nested_layers(
remove_tseqs(shared_and_diff_subtypes.diff_input))
num_sseq_layers_to_remove_inputs = max(0,
num_sseq_layers_inputs - 1)
num_sseq_layers_outputs = num_nested_layers(
remove_tseqs(shared_and_diff_subtypes.diff_output))
num_sseq_layers_to_remove_outputs = max(
0, num_sseq_layers_outputs - 1)
if remove_tseqs(
shared_and_diff_subtypes.shared_outer) != ST_Tombstone():
#num_sseq_layers_inputs += num_nested_layers(remove_tseqs(shared_and_diff_subtypes.shared_outer))
#num_sseq_layers_outputs += num_nested_layers(remove_tseqs(shared_and_diff_subtypes.shared_outer))
input_ports = flatten_ports(
transpose_outer_dimensions(
shared_and_diff_subtypes.shared_outer,
shared_and_diff_subtypes.diff_input, cls.I),
num_sseq_layers_to_remove_inputs)
output_ports = flatten_ports(
transpose_outer_dimensions(
shared_and_diff_subtypes.shared_outer,
shared_and_diff_subtypes.diff_output, cls.O),
num_sseq_layers_to_remove_outputs)
else:
input_ports = flatten_ports(cls.I,
num_sseq_layers_to_remove_inputs)
output_ports = flatten_ports(
cls.O, num_sseq_layers_to_remove_outputs)
# this is only used if the shared outer layers contains any sseqs
sseq_layers_to_flatten = max(
num_nested_layers(
remove_tseqs(shared_and_diff_subtypes.shared_outer)) - 1,
0)
for idx in range(len(rams)):
# wire input and bank to input sorting network
wire(write_bank_for_input_lane_luts[idx].data,
input_sorting_network.I[idx].bank)
#if idx == 0:
# wire(cls.first_valid, write_valid_for_bank_luts[idx].data)
if idx < t_in_diff.port_width():
# since the input_ports are lists, need to wire them individually to the sorting ports
if remove_tseqs(shared_and_diff_subtypes.shared_outer
) != ST_Tombstone():
cur_input_port = flatten_ports(input_ports[idx],
sseq_layers_to_flatten)
cur_sort_port = flatten_ports(
input_sorting_network.I[idx].val,
sseq_layers_to_flatten)
for i in range(len(cur_input_port)):
wire(cur_input_port[i], cur_sort_port[i])
else:
if num_sseq_layers_inputs == 0:
# input_ports will be an array of bits for 1 element
# if no sseq in t_in
wire(input_ports, input_sorting_network.I[idx].val)
else:
wire(input_ports[idx],
input_sorting_network.I[idx].val)
#wire(cls.ram_wr, input_sorting_network.O[idx].val)
#wire(cls.ram_rd, rams[idx].RDATA)
else:
zero_const = DefineCoreirConst(
ram_element_type.magma_repr().size(), 0)().O
cur_sn_input = input_sorting_network.I[idx].val
while len(cur_sn_input) != len(zero_const):
cur_sn_input = cur_sn_input[0]
wire(zero_const, cur_sn_input)
# wire input sorting network, write addr, and write valid luts to banks
wire(input_sorting_network.O[idx].val, rams[idx].WDATA)
wire(write_addr_for_bank_luts[idx].data, rams[idx].WADDR)
#wire(write_addr_for_bank_luts[idx].data[0], cls.addr_wr[idx])
if has_ce:
wire(write_valid_for_bank_luts[idx].data & bit(cls.CE),
rams[idx].WE)
else:
wire(write_valid_for_bank_luts[idx].data, rams[idx].WE)
# wire output sorting network, read addr, read bank, and read enable
wire(rams[idx].RDATA, output_sorting_network.I[idx].val)
wire(output_lane_for_bank_luts[idx].data,
output_sorting_network.I[idx].lane)
wire(read_addr_for_bank_luts[idx].data, rams[idx].RADDR)
#wire(read_addr_for_bank_luts[idx].data[0], cls.addr_rd[idx])
# ok to read invalid things, so in read value LUT
if has_ce:
wire(bit(cls.CE), rams[idx].RE)
else:
wire(DefineCoreirConst(1, 1)().O[0], rams[idx].RE)
if has_reset:
wire(cls.RESET, rams[idx].RESET)
# wire output sorting network value to output or term
if idx < t_out_diff.port_width():
# since the output_ports are lists, need to wire them individually to the sorting ports
if remove_tseqs(shared_and_diff_subtypes.shared_outer
) != ST_Tombstone():
cur_output_port = flatten_ports(
output_ports[idx], sseq_layers_to_flatten)
cur_sort_port = flatten_ports(
output_sorting_network.O[idx].val,
sseq_layers_to_flatten)
for i in range(len(cur_output_port)):
wire(cur_output_port[i], cur_sort_port[i])
else:
if num_sseq_layers_outputs == 0:
# output_ports will be an array of bits for 1 element
# if no sseq in t_out
wire(output_sorting_network.O[idx].val,
output_ports)
else:
wire(output_sorting_network.O[idx].val,
output_ports[idx])
else:
wire(output_sorting_network.O[idx].val,
TermAnyType(type(output_sorting_network.O[idx].val)))
# wire sorting networks bank/lane to term as not used on outputs, just used for sorting
wire(input_sorting_network.O[idx].bank,
TermAnyType(type(input_sorting_network.O[idx].bank)))
wire(output_sorting_network.O[idx].lane,
TermAnyType(type(output_sorting_network.O[idx].lane)))
@classmethod
def definition(io):
adders = [FullAdder() for _ in range(N)]
circ = m.braid(adders, foldargs={"cin": "cout"})
m.wire(io.a, circ.a)
m.wire(io.b, circ.b)
m.wire(io.cin, circ.cin)
m.wire(io.cout, circ.cout)
m.wire(io.out, circ.out)
return Adder
if __name__ == "__main__":
from magma.python_simulator import PythonSimulator
from magma.scope import Scope
from magma.bit_vector import BitVector
Adder4 = DefineAdder(4)
simulator = PythonSimulator(Adder4)
scope = Scope()
simulator.set_value(Adder4.a, scope,
BitVector(2, num_bits=4).as_bool_list())
simulator.set_value(Adder4.b, scope,
BitVector(3, num_bits=4).as_bool_list())
simulator.set_value(Adder4.cin, scope, True)
simulator.evaluate()
assert simulator.get_value(Adder4.out, scope) == int2seq(6, 4)
assert simulator.get_value(Adder4.cout, scope) == False
print("Success!")
from magma import *
from magma.bitutils import int2seq
from mantle.util.edge import falling, rising
from mantle import *
from rom import ROM16
from uart import UART
trigger = 1 # maybe tie to GPIO later
# ArduCAM start capture sequence
init = [
array(int2seq(0x8200, 16)), # Change MCU mode
array(int2seq(0x8401, 16)),
array(int2seq(0x8401, 16)),
array(int2seq(0x8402, 16)), # Start capture
array(int2seq(0x4100, 16)), # check capture completion flag
array(int2seq(0x4200, 16)),
array(int2seq(0x4300, 16)),
array(int2seq(0x4400, 16)), # Read image length
array(int2seq(0x3CFF, 16)),
array(int2seq(0x0000, 16)), # burst read
array(int2seq(0x0000, 16)),
array(int2seq(0x0000, 16)),
array(int2seq(0x0000, 16)),
array(int2seq(0x0000, 16)),
array(int2seq(0x0000, 16)),
array(int2seq(0x0000, 16))
]
# Read ROM unit
import magma as m
from magma.bitutils import int2seq
from mantle.util.edge import falling, rising
from mantle import I0, I1, I2, I3
import mantle
from rom import ROM16
from uart import UART
trigger = m.VCC # maybe tie to GPIO later
# ArduCAM start capture sequence
init = [
# Change MCU mode
m.array(int2seq(0x8200, 16)),
# Start capture
m.array(int2seq(0x8401, 16)),
m.array(int2seq(0x8401, 16)),
m.array(int2seq(0x8402, 16)),
# check capture completion flag
m.array(int2seq(0x4100, 16)),
# Read image length
m.array(int2seq(0x4200, 16)),
m.array(int2seq(0x4300, 16)),
m.array(int2seq(0x4400, 16)),
# burst read
m.array(int2seq(0x3CFF, 16)),
m.array(int2seq(0x0000, 16)),
m.array(int2seq(0x0000, 16)),
m.array(int2seq(0x0000, 16)),
m.array(int2seq(0x0000, 16)),
m.array(int2seq(0x0000, 16)),
import magma as m
from magma.bitutils import int2seq
import mantle
from loam.boards.icestick import IceStick
from rom import ROM
icestick = IceStick()
icestick.Clock.on()
icestick.TX.output().on()
main = icestick.main()
valid = 1
init = [m.array(int2seq(ord(c), 8)) for c in 'hello, world \r\n']
printf = mantle.Counter(4, has_ce=True)
rom = ROM(4, init, printf.O)
data = m.array([rom.O[7], rom.O[6], rom.O[5], rom.O[4],
rom.O[3], rom.O[2], rom.O[1], rom.O[0], 0])
counter = mantle.CounterModM(103, 8)
baud = counter.COUT
count = mantle.Counter(4, has_ce=True, has_reset=True)
decode = mantle.Decode(15, 4)
done = decode(count.O)
run = mantle.DFF(has_ce=True)
run_n = mantle.LUT3([0,0,1,0, 1,0,1,0])
