def test():
args = ['I', In(Bit), 'O', Out(Bit)]
args += ClockInterface(False, False, False)
testcircuit = DefineCircuit('TestCircuit', *args)
ff = PRIM_FF()
wire(testcircuit.I, ff.D)
wire(ff.Q, testcircuit.O)
EndCircuit()
sim = PythonSimulator(testcircuit, testcircuit.CLK)
sim.evaluate()
val = sim.get_value(testcircuit.O)
assert (val == False)
sim.advance()
val = sim.get_value(testcircuit.O)
assert (val == False)
sim.set_value(testcircuit.I, True)
sim.evaluate()
val = sim.get_value(testcircuit.O)
assert (val == False)
sim.advance()
val = sim.get_value(testcircuit.O)
assert (val == True)
sim.advance()
val = sim.get_value(testcircuit.O)
assert (val == True)
def test_shift_sim():
Shift = DefineLSL(8, 4)
lsl_sim = PythonSimulator(Shift)
I = BitVector(0x01, 8)
O = BitVector(0x10, 8)
lsl_sim.set_value(Shift.I, I)
lsl_sim.evaluate()
assert lsl_sim.get_value(Shift.O) == O
def test_rom():
main = DefineCircuit("test_romb", "RDATAOUT", Out(Bits(8)), "CLK",
In(Clock)) # FIXME: hack
romb = ROMB(512, 8, [0b00000001, 0b11111111] + [0] * 510)
wire(romb.RADDR, uint(1, 9))
wire(romb.RCLK, main.CLK)
wire(romb.RE, 1)
wire(romb.RDATA, main.RDATAOUT)
EndCircuit()
sim = PythonSimulator(main, clock=main.CLK)
sim.evaluate()
sim.advance(2)
assert sim.get_value(main.RDATAOUT) == BitVector(0b11111111, num_bits=8)
def test_ramb():
main = DefineCircuit("test_ramb",
"RDATA", Out(Bits(8)),
"WDATA", In(Bits(8)),
"WE", In(Bit),
"CLK", In(Clock))
ramb = RAMB(512, 8, [0b00000001, 0b11111111] + [0] * 510)
wire(ramb.RADDR, uint(1, 9))
wire(ramb.RCLK, main.CLK)
wire(ramb.RE, 1)
wire(ramb.WADDR, uint(1, 9))
wire(ramb.WCLK, main.CLK)
wire(ramb.WE, main.WE)
wire(ramb.RDATA, main.RDATA)
wire(ramb.WDATA, main.WDATA)
EndCircuit()
sim = PythonSimulator(main, clock=main.CLK)
sim.set_value(main.WE, False)
sim.evaluate()
sim.advance(2)
assert BitVector(sim.get_value(main.RDATA)) == BitVector(0b11111111, num_bits=8)
# Write 0xBE to WADDR = 1
sim.set_value(main.WE, True)
sim.set_value(main.WDATA, BitVector(0xBE, num_bits=8))
sim.advance(2)
# Read RADDR = 1 again
sim.set_value(main.WE, False)
sim.evaluate()
sim.advance(2)
assert BitVector(sim.get_value(main.RDATA)) == BitVector(0xBE, num_bits=8)
def test():
args = ['I0', In(Bit), 'I1', In(Bit), 'O',
Out(Bit)] + ClockInterface(False, False, False)
testcircuit = DefineCircuit('TestCircuit', *args)
andy = PRIM_AND()
ori = PRIM_OR()
ori2 = PRIM_OR()
n = PRIM_NOT()
wire(testcircuit.I0, andy.I0)
wire(testcircuit.I1, andy.I1)
wire(testcircuit.I0, ori.I0)
wire(testcircuit.I1, n.I)
wire(n.O, ori.I1)
wire(ori.O, ori2.I0)
wire(andy.O, ori2.I1)
wire(ori2.O, testcircuit.O)
EndCircuit()
sim = PythonSimulator(testcircuit)
sim.evaluate()
v = sim.get_value(testcircuit.O)
assert v == True
sim.set_value(testcircuit.I1, True)
sim.evaluate()
v = sim.get_value(testcircuit.O)
assert v == False
sim.set_value(testcircuit.I0, True)
sim.evaluate()
v = sim.get_value(testcircuit.O)
assert v == True
def clb(a, b, c, d):
return (a & b) | (~c & d)
T = UInt(16)
class Combinational(Circuit):
name = "Combinational"
IO = ["a", In(T), "b", In(T), "c", Out(T)]
@classmethod
def definition(io):
wire(clb(io.a, io.b, io.a, io.b), io.c)
# In[3]:
from magma.simulator import PythonSimulator
from magma.bit_vector import BitVector
simulator = PythonSimulator(Combinational)
a = BitVector(148, num_bits=16)
b = BitVector(41, num_bits=16)
simulator.set_value(Combinational.a, a)
simulator.set_value(Combinational.b, b)
simulator.evaluate()
assert simulator.get_value(Combinational.c) == clb(a, b, a, b)
print("Success!")
def test(capsys):
def get_out(capsys):
out, err = capsys.readouterr()
assert (err == "")
return out.rstrip()
def FFs(n):
return [PRIM_FF() for i in range(n)]
def Register(n):
args = ["I", In(Array(n, Bit)), "O",
Out(Array(n, Bit))] + ClockInterface(False, False, False)
RegCircuit = DefineCircuit('Register' + str(n), *args)
ffs = join(FFs(n))
wire(RegCircuit.I, ffs.D)
wire(ffs.Q, RegCircuit.O)
EndCircuit()
return RegCircuit()
def IncOne(n):
def sim_inc_one(self, value_store, state_store):
I = value_store.get_value(self.I)
n = len(I)
val = seq2int(I) + 1
cout = val > ((1 << n) - 1)
val = val % (1 << n)
seq = int2seq(val, len(I))
seq = [bool(s) for s in seq]
value_store.set_value(self.O, seq)
value_store.set_value(self.COUT, cout)
args = [
"I",
In(Array(n, Bit)), "O",
Out(Array(n, Bit)), "COUT",
Out(Bit)
]
return DeclareCircuit('IncOne' + str(n),
*args,
stateful=False,
primitive=True,
simulate=sim_inc_one)()
def TestCounter(n):
args = []
args += ["O", Array(n, Out(Bit))]
args += ["COUT", Out(Bit)]
args += ClockInterface(False, False, False)
Counter = DefineCircuit('Counter' + str(n), *args)
inc = IncOne(n)
reg = Register(n)
wire(reg.O, inc.I)
wire(inc.O, reg.I)
wire(reg.O, Counter.O)
wire(inc.COUT, Counter.COUT)
wireclock(Counter, reg)
EndCircuit()
return Counter()
args = ['O', Array(5, Out(Bit)), 'COUT', Out(Bit)]
args += ClockInterface(False, False, False)
testcircuit = DefineCircuit('Test', *args)
counter = TestCounter(5)
wire(counter.O, testcircuit.O)
wire(counter.COUT, testcircuit.COUT)
EndCircuit()
sim = PythonSimulator(testcircuit, testcircuit.CLK)
DebugNamePass(testcircuit).run()
console = SimulationConsole(testcircuit, sim)
sim.evaluate()
console.runcmd("p self.O")
out, err = capsys.readouterr()
assert (out.rstrip() == "0")
console.runcmd("p self.idontexist")
out, err = capsys.readouterr()
assert (err != "")
assert (out == "")
console.runcmd("next")
out, err = capsys.readouterr()
assert (err == "")
assert (out == "")
console.runcmd("p self.O")
assert get_out(capsys) == "1"
console.runcmd("next")
console.runcmd("p self.O")
assert get_out(capsys) == "2"
console.runcmd("p counter.O")
assert get_out(capsys) == "2"
console.runcmd("p counter.reg.O")
assert get_out(capsys) == "2"
class PythonTester(InteractiveTester):
def __init__(self, *args, **kwargs):
super().__init__(*args, **kwargs)
self.simulator = PythonSimulator(self._circuit, self.clock)
def eval(self):
self.simulator.evaluate()
def _set_value(self, port, value):
port, scope = _process_port(port)
self.simulator.set_value(port, value, scope)
def _poke(self, port, value, delay=None):
if delay is not None:
raise NotImplementedError("delay is not support in Python "
"simulator")
type_ = get_port_type(port)
self._set_value(port, value)
def process_result(self, type_, result):
if issubclass(type_, m.Digital):
return Bit(result)
if issubclass(type_, m.Bits):
return BitVector[len(type_)](result)
if is_recursive_type(type_):
return BitVector[len(type_)](result)
return result
def _get_value(self, port):
port, scope = _process_port(port)
if isinstance(port, (int, BitVector, Bit, list)):
return port
result = self.simulator.get_value(port, scope)
return self.process_result(type(port), result)
def _expect(self, port, value, strict=None, caller=None, **kwargs):
got = self._get_value(port)
port, scope = _process_port(port)
value = make_value(type(port), value)
expected = self._get_value(value)
check(got, port, expected)
def peek(self, port):
return self._get_value(port)
def print(self, format_str, *args):
got = [self._get_value(port) for port in args]
values = ()
for value, port in zip(got, args):
if (isinstance(port, m.Array) and issubclass(port.T, m.Digital)):
value = BitVector[len(port)](value).as_uint()
elif isinstance(port, m.Array):
raise NotImplementedError("Printing complex nested " "arrays")
values += (value, )
print(format_str % values, end="")
def assert_(self, expr, msg=""):
assert expr, msg
def delay(self, time):
raise NotImplementedError()
def get_value(self, port):
raise NotImplementedError()
def step(self, steps=1):
"""
Step the clock `steps` times.
"""
self.eval()
self.simulator.advance(steps)
def wait_until_low(self, signal):
while self.peek(signal):
self.step()
def wait_until_high(self, signal):
while ~self.peek(signal):
self.step()
def __call__(self, *args, **kwargs):
result = super().__call__(*args, **kwargs)
if isinstance(result, tuple):
return tuple(self.peek(r.select_path) for r in result)
return self.peek(result.select_path)
