def do_waveform(self, arg):
if not arg:
print_err('Please a provide wire')
return
try:
waveme, scope = self.parse_circuit(arg)
except Exception as e:
print_err("Invalid argument for waveform: {}".format(e))
return
if not isinstance(waveme, BitType) and not isinstance(
waveme, ArrayType):
print_err("Can only provide waveforms for wires")
return
labels = [arg]
signals = []
for i in range(self.cycles - 1):
val = self.simulator.get_value(waveme, scope)
signals.insert(0, [seq2int(val)])
self.simulator.rewind(2)
for i in range(self.cycles - 1):
self.simulator.step()
self.simulator.step()
waveform(signals, labels)
# In[2]:
m.compile("build/FullAdder", FullAdder, output="coreir")
get_ipython().magic('cat build/FullAdder.json')
# In[3]:
m.compile("build/FullAdder", FullAdder, output="coreir-verilog")
get_ipython().magic('cat build/FullAdder.v')
# In[4]:
from fault.test_vectors import generate_simulator_test_vectors
from bit_vector import BitVector
test_vectors_raw = [[0, 0, 0, 0, 0], [0, 0, 1, 1, 0], [0, 1, 0, 1, 0],
[0, 1, 1, 0, 1], [1, 0, 0, 1, 0], [1, 0, 1, 0, 1],
[1, 1, 0, 0, 1], [1, 1, 1, 1, 1]]
test_vectors = [[BitVector(x) for x in test_vector]
for test_vector in test_vectors_raw]
tests = generate_simulator_test_vectors(FullAdder, flatten=False)
print("Success" if tests == test_vectors else "Failure")
# In[5]:
from magma.waveform import waveform
waveform(test_vectors_raw, ["a", "b", "cin", "sum", "cout"])
_sum = io.a ^ io.b ^ io.cin
wire(_sum, io.out)
# Generate the carry
carry = (io.a & io.b) | (io.b & io.cin) | (io.a & io.cin)
wire(carry, io.cout)
# In[2]:
from magma.backend.verilog import compile as compile_verilog
print(compile_verilog(FullAdder))
# In[3]:
from magma.simulator.python_simulator import testvectors
test_vectors = [[0, 0, 0, 0, 0], [0, 0, 1, 1, 0], [0, 1, 0, 1, 0],
[0, 1, 1, 0, 1], [1, 0, 0, 1, 0], [1, 0, 1, 0, 1],
[1, 1, 0, 0, 1], [1, 1, 1, 1, 1]]
tests = testvectors(FullAdder)
print(tests)
print("Success" if tests == test_vectors else "Failure")
# In[4]:
from magma.waveform import waveform
waveform(tests, ["a", "b", "cin", "sum", "cout"])
DefineShiftRegister(2, has_ce=True),
output="coreir")
get_ipython().magic('cat build/DefineShiftRegister.json')
# In[3]:
from magma.simulator.coreir_simulator import CoreIRSimulator
from bit_vector import BitVector
N = 3
ShiftRegisterNCE = DefineShiftRegister(N, has_ce=True)
simulator = CoreIRSimulator(ShiftRegisterNCE, clock=ShiftRegisterNCE.CLK)
outputs = []
for j in range(2):
simulator.advance()
for I, enable in [(1, 1), (0, 1), (1, 1), (0, 1), (1, 0), (0, 0), (1, 1),
(1, 1), (1, 1), (1, 1)]:
simulator.set_value(ShiftRegisterNCE.I, bool(I))
simulator.set_value(ShiftRegisterNCE.CE, bool(enable))
for j in range(2):
simulator.advance()
O = simulator.get_value(ShiftRegisterNCE.O)
CLK = simulator.get_value(ShiftRegisterNCE.CLK)
outputs.append([O, I, enable, CLK])
# In[4]:
from magma.waveform import waveform
waveform(outputs, ["O", "I", "CE", "CLK"])