def test_bit_term():
assert repr(CorebitTerm) == """\
corebit_term = DefineCircuit("corebit_term", "in", In(Bit))
EndCircuit()"""
compile("build/test_bit_term", CorebitTerm, output="coreir")
assert check_files_equal(__file__, "build/test_bit_term.json",
"gold/test_bit_term.json")
def test_two_ops():
Top = m.DefineCircuit("test_two_ops", "I0", m.In(m.UInt(8)), "I1",
m.In(m.UInt(8)), "O", m.Out(m.UInt(8)))
result = Top.I0 + Top.I1 - Top.I0
m.wire(result, Top.O)
m.EndCircuit()
m.compile("test_two_ops", Top, output="coreir-verilog", inline=True)
# assert check_files_equal(__file__, "build/test_two_ops.v",
# "gold/test_two_ops.v")
# Roundabout way to do this since we can't pass the --inline flag through
# fault's tester interface yet
tester = fault.Tester(Top)
for i in range(0, 16):
I0 = fault.random.random_bv(8)
I1 = fault.random.random_bv(8)
tester.poke(Top.I0, I0)
tester.poke(Top.I1, I1)
tester.eval()
tester.expect(Top.O, I0 + I1 - I0)
tester.compile_and_run(target="verilator",
skip_compile=True,
directory=".")
def __init__(self,
circuit,
circuit_name=None,
directory="build/",
skip_compile=False,
include_verilog_libraries=None,
magma_output="verilog",
magma_opts=None,
use_kratos=False,
value_file_name='get_value_file.txt'):
super().__init__(circuit)
if circuit_name is None:
circuit_name = self.circuit.name
self.circuit_name = circuit_name
self.directory = Path(directory)
os.makedirs(directory, exist_ok=True)
self.skip_compile = skip_compile
if include_verilog_libraries is None:
include_verilog_libraries = []
self.include_verilog_libraries = include_verilog_libraries
self.magma_output = magma_output
self.magma_opts = magma_opts if magma_opts is not None else {}
if hasattr(circuit, "verilog_file_name") and \
os.path.splitext(circuit.verilog_file_name)[-1] == ".sv" or \
use_kratos:
suffix = "sv"
else:
suffix = "v"
self.verilog_file = Path(f"{self.circuit_name}.{suffix}")
# Optionally compile this module to verilog first.
if not self.skip_compile:
prefix = os.path.splitext(self.directory / self.verilog_file)[0]
m.compile(prefix,
self.circuit,
output=self.magma_output,
**self.magma_opts)
if use_kratos:
# kratos generates SystemVerilog file
# Until magma/coreir can generate sv suffix, we have to move
# the files around
os.rename(prefix + ".v", prefix + ".sv")
if not (self.directory / self.verilog_file).is_file():
raise Exception(f"Compiling {self.circuit} failed")
self.assumptions = []
self.guarantees = []
# set up value file for storing user-accessible resuls
value_file_path = (Path(self.directory) / value_file_name).resolve()
self.value_file = File(name=str(value_file_path),
tester=None,
mode='w',
chunk_size=None,
endianness=None)
def test_simple_def(target, suffix):
m.set_codegen_debug_info(True)
And2 = m.DeclareCircuit('And2', "I0", m.In(m.Bit), "I1", m.In(m.Bit), "O",
m.Out(m.Bit))
main = m.DefineCircuit("main", "I", m.In(m.Bits[2]), "O", m.Out(m.Bit))
and2 = And2()
m.wire(main.I[0], and2.I0)
m.wire(main.I[1], and2.I1)
m.wire(and2.O, main.O)
m.EndCircuit()
m.compile("build/test_simple_def", main, output=target)
assert check_files_equal(__file__, f"build/test_simple_def.{suffix}",
f"gold/test_simple_def.{suffix}")
# Check that the subclassing pattern produces the same annotations
class Main(m.Circuit):
IO = ["I", m.In(m.Bits[2]), "O", m.Out(m.Bit)]
@classmethod
def definition(io):
and2 = And2()
m.wire(io.I[0], and2.I0)
m.wire(io.I[1], and2.I1)
m.wire(and2.O, io.O)
# Create a fresh context for second compilation.
m.compile("build/test_simple_def_class", Main, output=target)
m.set_codegen_debug_info(False)
assert check_files_equal(__file__, f"build/test_simple_def_class.{suffix}",
f"gold/test_simple_def_class.{suffix}")
def test_shift_register():
N = 4
Register4 = DefineRegister(4)
T = m.Bits[ N ]
class ShiftRegister(m.Circuit):
name = "ShiftRegister"
IO = ["I", m.In(T), "O", m.Out(T), "CLK", m.In(m.Clock)]
@classmethod
def definition(io):
regs = [Register4() for _ in range(N)]
m.wire(io.I, regs[0].I)
m.fold(regs, foldargs={"I": "O"})
m.wire(regs[-1].O, io.O)
simulator = PythonSimulator(ShiftRegister, clock=ShiftRegister.CLK)
expected = [0, 0, 0] + list(range(0, 1 << N, 3))[:-3]
actual = []
for i in range(0, 1 << N, 3):
simulator.set_value(ShiftRegister.I, i)
simulator.advance(2)
actual.append(simulator.get_value(ShiftRegister.O))
assert actual == expected
m.compile("build/ShiftRegister", ShiftRegister, output="coreir")
assert m.testing.check_files_equal(__file__, "build/ShiftRegister.json",
"gold/ShiftRegister.json")
def test_verilator_trace():
circ = TestBasicClkCircuit
actions = [
Poke(circ.I, 0),
Print("%x", circ.I),
Expect(circ.O, 0),
Poke(circ.CLK, 0),
Print("%x", circ.O),
Step(circ.CLK, 1),
Poke(circ.I, BitVector[1](1)),
Eval(),
Print("%x", circ.O),
]
flags = ["-Wno-lint", "--trace"]
with tempfile.TemporaryDirectory(dir=".") as tempdir:
assert not os.path.isfile(f"{tempdir}/logs/BasicClkCircuit.vcd"), \
"Expected logs to be empty"
m.compile(f"{tempdir}/{circ.name}", circ,
output="coreir-verilog")
target = fault.verilator_target.VerilatorTarget(
circ, directory=f"{tempdir}/",
flags=flags, skip_compile=True)
target.run(actions)
assert os.path.isfile(f"{tempdir}/logs/BasicClkCircuit.vcd"), \
"Expected VCD to exist"
def test_new_types(output):
# TODO: Make it easier to do a type alias like this (for a parametrized type)
def Coordinate(num_bits):
return m.Bits[num_bits]
# Parametrized types should be implemented using a type constructure
# TODO: Add suport for isinstance(t, Polygon), need to rework to use class
# structure or at least autogenerate a PolygonType (or document how to
# subclass and create a new Type/Kind)
def Point2D(num_bits):
return m.Tuple(x=Coordinate(num_bits), y=Coordinate(num_bits))
def Polygon(num_vertices, num_bits):
return m.Array[num_vertices, Point2D(num_bits)]
class TestCircuit(m.Circuit):
IO = [
"I", m.In(Polygon(12, 3)),
"O", m.Out(Polygon(12, 3))
]
@classmethod
def definition(io):
m.wire(io.I, io.O)
suffix = 'v' if output == 'coreir-verilog' else 'json'
m.compile('build/test_new_types', TestCircuit, output=output)
assert check_files_equal(__file__, f"build/test_new_types.{suffix}",
f"gold/test_new_types.{suffix}")
def test_declare_generator():
DefineSmax = DeclareCoreIRGenerator(lib="commonlib", name="smax")
width = 16
class LinkerTest(m.Circuit):
name = "LinkerTest0"
IO = [
"I0",
m.In(m.Bits[width]), "I1",
m.In(m.Bits[width]), "O",
m.Out(m.Bits[width])
]
@classmethod
def definition(self):
Smax = DefineSmax(width=width)
smax = Smax()
m.wire(self.I0, smax.in0)
m.wire(self.I1, smax.in1)
m.wire(self.O, smax.out)
dir_path = os.path.dirname(os.path.realpath(__file__))
m.compile(os.path.join(dir_path, "build/linker_test0"),
LinkerTest,
output="coreir")
assert check_files_equal(__file__, "build/linker_test0.json",
"gold/linker_test0.json")
def test_sipo_basic():
class test_sipo_basic(m.Circuit):
io = m.IO(I=m.In(m.Bit), O=m.Out(m.Bits[5])) + m.ClockIO()
io.O @= SIPO(5, m.Bit)()(io.I)
m.compile("build/test_sipo_basic", test_sipo_basic)
assert check_files_equal(__file__, f"build/test_sipo_basic.v",
f"gold/test_sipo_basic.v")
tester = fault.SynchronousTester(test_sipo_basic, test_sipo_basic.CLK)
tester.circuit.I = 1
tester.advance_cycle()
tester.circuit.O.expect(0b00001)
tester.advance_cycle()
tester.circuit.O.expect(0b00011)
tester.circuit.I = 0
tester.advance_cycle()
tester.circuit.O.expect(0b00110)
tester.circuit.I = 1
tester.advance_cycle()
tester.circuit.O.expect(0b01101)
tester.circuit.I = 0
tester.advance_cycle()
tester.circuit.O.expect(0b11010)
tester.compile_and_run("verilator",
skip_compile=True,
directory=os.path.join(os.path.dirname(__file__),
"build"))
def test_ram():
main = m.DefineCircuit("main", "rdata", m.Out(m.Bit), "CLKIN",
m.In(m.Clock))
ram = mantle.RAM(4, 1, name="ram")
waddr = mantle.Counter(2, cout=False)
wdata = mantle.Counter(1, cout=False)
we = 1
raddr = mantle.Counter(2, cout=False)
ram(raddr, waddr, wdata, we, CLK=main.CLKIN)
m.wire(ram.RDATA[0], main.rdata)
m.EndDefine()
if m.mantle_target == "coreir":
output = "coreir"
suffix = "json"
else:
output = "verilog"
suffix = "v"
m.compile(f"build/test_common_ram_{m.mantle_target}", main, output)
assert check_files_equal(
__file__, f"build/test_common_ram_{m.mantle_target}.{suffix}",
f"gold/test_common_ram_{m.mantle_target}.{suffix}")
def test_const():
Const8 = DefineCoreirConst(width=4, value=8)
assert repr(Const8) == """\
coreir_const48 = DeclareCircuit("coreir_const48", "O", Out(Bits(4)))"""
compile("build/test_const", wrap(Const8), output="coreir")
assert check_files_equal(__file__, "build/test_const.json",
"gold/test_const.json")
def __init__(self, circuit, circuit_name=None, directory="build/",
skip_compile=False, include_verilog_libraries=[],
magma_output="verilog", magma_opts={}):
super().__init__(circuit)
if circuit_name is None:
self.circuit_name = self.circuit.name
else:
self.circuit_name = circuit_name
self.directory = Path(directory)
self.skip_compile = skip_compile
self.include_verilog_libraries = include_verilog_libraries
self.magma_output = magma_output
self.magma_opts = magma_opts
if hasattr(circuit, "verilog_file_name") and \
os.path.splitext(circuit.verilog_file_name)[-1] == ".sv":
suffix = "sv"
else:
suffix = "v"
self.verilog_file = Path(f"{self.circuit_name}.{suffix}")
# Optionally compile this module to verilog first.
if not self.skip_compile:
prefix = os.path.splitext(self.directory / self.verilog_file)[0]
m.compile(prefix, self.circuit, output=self.magma_output,
**self.magma_opts)
if not (self.directory / self.verilog_file).is_file():
raise Exception(f"Compiling {self.circuit} failed")
def com(Test, name):
from magma.testing import check_files_equal
name = f'test_{name}'
build = f'build/{name}'
gold = f'gold/{name}'
m.compile(build, Test, output="verilog")
assert check_files_equal(__file__, build + '.v', gold + '.v')
def test_for_loop_def(target, suffix):
m.set_codegen_debug_info(True)
And2 = m.DeclareCircuit('And2', "I0", m.In(m.Bit), "I1", m.In(m.Bit), "O",
m.Out(m.Bit))
main = m.DefineCircuit("main", "I", m.In(m.Bits[2]), "O", m.Out(m.Bit))
and2_prev = None
for i in range(0, 4):
and2 = And2()
if i == 0:
m.wire(main.I[0], and2.I0)
m.wire(main.I[1], and2.I1)
else:
m.wire(and2_prev.O, and2.I0)
m.wire(main.I[1], and2.I1)
and2_prev = and2
m.wire(and2.O, main.O)
m.EndCircuit()
m.compile("build/test_for_loop_def", main, output=target)
m.set_codegen_debug_info(False)
assert check_files_equal(__file__, f"build/test_for_loop_def.{suffix}",
f"gold/test_for_loop_def.{suffix}")
def test_interleaved_instance_wiring(target, suffix):
m.set_codegen_debug_info(True)
And2 = m.DeclareCircuit('And2', "I0", m.In(m.Bit), "I1", m.In(m.Bit), "O",
m.Out(m.Bit))
main = m.DefineCircuit("main", "I", m.In(m.Bits[2]), "O", m.Out(m.Bit))
and2_0 = And2()
and2_1 = And2()
m.wire(main.I[0], and2_0.I0)
m.wire(main.I[1], and2_0.I1)
m.wire(and2_0.O, and2_1.I0)
m.wire(main.I[1], and2_1.I1)
and2_2 = And2()
m.wire(and2_1.O, and2_2.I0)
m.wire(main.I[0], and2_2.I1)
m.wire(and2_2.O, main.O)
m.EndCircuit()
m.compile("build/test_interleaved_instance_wiring", main, output=target)
m.set_codegen_debug_info(False)
assert check_files_equal(
__file__, f"build/test_interleaved_instance_wiring.{suffix}",
f"gold/test_interleaved_instance_wiring.{suffix}")
def test_coreir_wrap(T):
def define_wrap(type_, type_name, in_type):
def sim_wrap(self, value_store, state_store):
input_val = value_store.get_value(getattr(self, "in"))
value_store.set_value(self.out, input_val)
return DeclareCircuit(
f'coreir_wrap{type_name}',
"in", In(in_type), "out", Out(type_),
coreir_genargs = {"type": type_},
coreir_name="wrap",
coreir_lib="coreir",
simulate=sim_wrap
)
foo = DefineCircuit("foo", "r", In(T))
EndCircuit()
top = DefineCircuit("top", "O", Out(Bit))
foo_inst = foo()
wrap = define_wrap(T, "Bit", Bit)()
wire(bit(0), wrap.interface.ports["in"])
wire(wrap.out, foo_inst.r)
wire(bit(0), top.O)
EndCircuit()
with tempfile.TemporaryDirectory() as tempdir:
filename = f"{tempdir}/top"
compile(filename, top, output="coreir")
got = open(f"{filename}.json").read()
expected_filename = f"tests/test_type/test_coreir_wrap_golden_{T}.json"
expected = open(expected_filename).read()
assert got == expected
def test_config_register():
WIDTH = 32
ADDR_WIDTH = 8
ADDR_VALUE = 4
# Check that compilation to CoreIR works. Delete JSON file afterwards.
cr = define_config_register(WIDTH, m.bits(ADDR_VALUE, ADDR_WIDTH), True)
m.compile("config_register", cr, output='coreir')
gold_check = check_files_equal("config_register.json",
"test_common/gold/config_register.json")
assert gold_check
res = os.system("\\rm config_register.json")
assert res == 0
# Check the module against a simple simulation.
simulator = CoreIRSimulator(cr, clock=cr.CLK)
def reg_value():
return simulator.get_value(cr.O)
def step(I, addr):
simulator.set_value(cr.I, I)
simulator.set_value(cr.addr, addr)
simulator.set_value(cr.CE, 1)
simulator.advance(2)
return reg_value()
assert BitVector(reg_value()) == BitVector(0, WIDTH)
sequence = [(0, 0, 0), (12, 4, 12), (0, 0, 12), (9, 4, 9)]
for (I, addr, out_expected) in sequence:
out = step(BitVector(I, WIDTH), BitVector(addr, ADDR_WIDTH))
assert BitVector(out) == BitVector(out_expected, WIDTH)
def test_binary_primitive(binary_primitive, width):
primitive_name, primitive_op, signed = binary_primitive
prim = m.DeclareCircuit(f"primitive_name",
"in0",
m.In(m.Array(width, m.Bit)),
"in1",
m.In(m.Array(width, m.Bit)),
"out",
m.Out(m.Array(width, m.Bit)),
coreir_lib="coreir",
coreir_name=primitive_name,
coreir_genargs={"width": width})
circ = m.DefineCircuit(f"DesignTop", "I0", m.In(m.Array(width, m.Bit)),
"I1", m.In(m.Array(width, m.Bit)), "O",
m.Out(m.Array(width, m.Bit)))
inst = prim()
m.wire(circ.I0, inst.in0)
m.wire(circ.I1, inst.in1)
m.wire(circ.O, inst.out)
m.EndDefine()
m.compile(f"build/{primitive_name}", circ, output="coreir")
dir_path = os.path.dirname(os.path.realpath(__file__))
result = delegator.run(
f"CGRAMapper/bin/cgra-mapper build/{primitive_name}.json build/{primitive_name}_mapped.json",
cwd=dir_path)
assert not result.return_code, result.out + "\n" + result.err
result = delegator.run(f"./CGRAGenerator/bin/generate.csh")
assert not result.return_code, result.out + "\n" + result.err
result = delegator.run(
f"CGRAGenerator/bitstream/bsbuilder/serpent.csh build/{primitive_name}_mapped.json -cgra_info CGRAGenerator/hardware/generator_z/top/cgra_info.txt -o build/{primitive_name}_mapped_annotated"
)
assert not result.return_code, result.out + "\n" + result.err
def test_bit_const():
BitConst = DefineCorebitConst(value=1)
assert repr(BitConst) == """\
corebit_const1 = DeclareCircuit("corebit_const1", "O", Out(Bit))"""
compile("build/test_bit_const", wrap(BitConst), output="coreir")
assert check_files_equal(__file__, "build/test_bit_const.json",
"gold/test_bit_const.json")
def test_compile(caplog):
And2 = m.DeclareCircuit('And2', "I0", m.In(m.Bit), "I1", m.In(m.Bit), "O",
m.Out(m.Bit))
# Make it a mock mantle module
class MockMantle:
pass
MockMantle.__name__ = "mantle.coreir.arith"
And2.debug_info = m.debug.debug_info(And2.debug_info.filename,
And2.debug_info.lineno, MockMantle)
main = m.DefineCircuit("main", "I", m.In(m.Bits[2]), "O", m.Out(m.Bit))
and2 = And2()
m.wire(main.I[0], and2.I0)
m.wire(main.I[1], and2.I1)
m.wire(and2.O, main.O)
m.EndCircuit()
m.compile("build/test_compile_coreir_verilog", main)
assert check_files_equal(__file__, "build/test_compile_coreir_verilog.v",
"gold/test_compile_coreir_verilog.v")
assert caplog.records[
0].msg == "`m.compile` called with `output == verilog` and `m.mantle_target == \"coreir\"` and mantle has been imported, When generating verilog from circuits from the \"coreir\" mantle target, you should set `output=\"coreir-verilog\"`. Doing this automatically."
def test_bit_term():
CorebitTerm = DefineCorebitTerm()
assert repr(CorebitTerm) == """\
corebit_term = DeclareCircuit("corebit_term", "I", In(Bit))"""
compile("build/test_bit_term", wrap(CorebitTerm), output="coreir")
assert check_files_equal(__file__, "build/test_bit_term.json",
"gold/test_bit_term.json")
def test_binary_op(op, N, T, TType):
"""
Tests mantle.operator by using the operator.{op.name} method directly and
using the overloaded {op.operator} if it is not None.
"""
if op.name in ["mul"] and T not in (m.UInt, m.SInt):
pytest.skip(f"{op.name} only defined for m.UInt and m.SInt")
if op.name in ["udiv", "umod"] and T != m.UInt:
pytest.skip(f"{op.name} only defined for m.UInt")
elif op.name in ["sdiv", "smod"] and T != m.SInt:
pytest.skip(f"{op.name} only defined for m.SInt")
def to_str(x):
if callable(x):
return x.__name__
return str(x)
_name = "TestsCircuit_" + \
"_".join(to_str(x) for x in (op.name, N, T, TType))
# List of comparison ops so we can special case them (output type and
# wiring 0)
comparisons = ["lt", "le", "gt", "ge"]
if op.name in comparisons + ["eq", "ne"]:
out_T = m.Out(m.Bit)
expected_res_type = m.BitType
else:
out_T = m.Out(T(N))
expected_res_type = TType
class TestCircuit(m.Circuit):
name = _name
IO = [
"I0",
m.In(T(N)), "I1",
m.In(T(N)), "O0", out_T, "O1", out_T, "O2", out_T
]
@classmethod
def definition(io):
# Test using the method directly
res = getattr(mantle, op.name)(io.I0, io.I1)
assert isinstance(res, expected_res_type), type(res)
m.wire(res, io.O0)
# Test using the operator if it exists, otherwise wire 0 to O1
if op.operator is None or (op.name in ["sub", "add"] + comparisons
and T == m.Bits):
if op.name in comparisons:
m.wire(0, io.O1)
else:
m.wire(m.bits(0, N), io.O1)
else:
res_operator = eval(f"io.I0 {op.operator} io.I1")
m.wire(res_operator, io.O1)
# Test integer promotion
res = getattr(mantle, op.name)(io.I0, 1)
m.wire(res, io.O2)
m.compile(f'build/{_name}', TestCircuit, output="coreir")
assert check_files_equal(__file__, f"build/{_name}.json",
f"gold/{_name}.json")
def test_two_ports(backend):
height = 4
data_width = 4
addr_width = m.bitutils.clog2(height)
class _Main(m.Circuit):
name = f"test_regfile_two_ports_{backend}"
io = m.IO(write_addr0=m.In(m.Bits[addr_width]),
write_data0=m.In(m.Bits[data_width]),
write_addr1=m.In(m.Bits[addr_width]),
write_data1=m.In(m.Bits[data_width]),
read_addr0=m.In(m.Bits[addr_width]),
read_data0=m.Out(m.Bits[data_width]),
read_addr1=m.In(m.Bits[addr_width]),
read_data1=m.Out(
m.Bits[data_width])) + m.ClockIO(has_async_reset=True)
reg_file = mantle.RegFileBuilder("my_regfile",
height,
data_width,
backend=backend)
reg_file[io.write_addr0] = io.write_data0
io.read_data0 @= reg_file[io.read_addr0]
reg_file[io.write_addr1] = io.write_data1
io.read_data1 @= reg_file[io.read_addr1]
m.compile(f"build/test_regfile_two_ports_{backend}", _Main)
assert check_files_equal(__file__,
f"build/test_regfile_two_ports_{backend}.v",
f"gold/test_regfile_two_ports_{backend}.v")
tester = fault.Tester(_Main, _Main.CLK)
tester.circuit.CLK = 0
for i in range(4):
tester.circuit.write_addr0 = i
tester.circuit.write_data0 = 3 - i
tester.circuit.write_addr1 = 3 - i
tester.circuit.write_data1 = i
tester.step(2)
for i in range(4):
tester.circuit.read_addr0 = i
tester.circuit.read_addr1 = 3 - i
tester.eval()
tester.circuit.read_data0.expect(3 - i)
tester.circuit.read_data1.expect(i)
# Test priority.
tester.circuit.write_addr0 = 3
tester.circuit.write_data0 = 3
tester.circuit.write_addr1 = 3
tester.circuit.write_data1 = 4
tester.step(2)
tester.circuit.read_addr0 = 3
tester.eval()
tester.circuit.read_data0.expect(4)
build_dir = os.path.join(os.path.dirname(__file__), "build")
tester.compile_and_run(target="verilator",
directory=build_dir,
skip_compile=True,
flags=["-Wno-unused", "-Wno-undriven"])
def test_1x1():
# this is all PE
interconnect = create_cgra(1, 1, IOSide.None_, num_tracks=3, mem_ratio=(0, 1))
circuit = interconnect.circuit()
with tempfile.TemporaryDirectory() as temp:
filename = os.path.join(temp, "1x1")
magma.compile(filename, circuit)
assert os.path.isfile(filename + ".v")
def com(Test, name):
import magma
from magma import compile
from magma.testing import check_files_equal
name = f'test_{magma.mantle_target}_{name}'
build = 'build/' + name
gold = 'gold/' + name
compile(build, Test)
def com(Test, name):
from magma import compile
from magma.testing import check_files_equal
name = 'test_{}'.format(name)
build = 'build/' + name
gold = 'gold/' + name
compile(build, Test)
assert check_files_equal(__file__, build + '.v', gold + '.v')
def test_simple_top():
Top = m.DefineCircuit("Top", "I0", m.In(m.UInt(8)), "I1", m.In(m.UInt(8)),
"O", m.Out(m.UInt(8)))
sum_ = Top.I0 + Top.I1
m.wire(sum_, Top.O)
m.EndCircuit()
m.compile("test_simple_top", Top, output="coreir-verilog", inline=True)
def test_bit_const():
BitConst = DefineCorebitConst(value=1)
assert repr(BitConst) == """\
corebit_const1 = DefineCircuit("corebit_const1", "out", Out(Bit))
wire(1, corebit_const1.out)
EndCircuit()"""
compile("build/test_bit_const", BitConst, output="coreir")
assert check_files_equal(__file__, "build/test_bit_const.json",
"gold/test_bit_const.json")
def test_verilator_peeks():
circ = common.TestBasicCircuit
actions = [Poke(circ.I, 1), Expect(circ.O, Peek(circ.O))]
flags = ["-Wno-lint"]
with tempfile.TemporaryDirectory() as tempdir:
m.compile(f"{tempdir}/{circ.name}", circ, output="coreir-verilog")
target = fault.verilator_target.VerilatorTarget(
circ, directory=f"{tempdir}/", flags=flags, skip_compile=True)
target.run(actions)
def gen_verilog():
arch = read_arch("outputs/PE.json")
graph_arch(arch)
PE_fc = pe_arch_closure(arch)
PE = PE_fc(family.MagmaFamily())
if not os.path.exists('outputs/verilog'):
os.makedirs('outputs/verilog')
m.compile(f"outputs/verilog/PE", PE, output="coreir-verilog")
IOL.append("process_input")
IOL.append(m.In(rigelTypeToMagmaType(itype)))
IOL.append("process_output")
IOL.append(m.Out(rigelTypeToMagmaType(otype)))
class NewMod(m.Circuit):
name = mod.name
IO = IOL
NewMod.verilogFile = mod.toVerilog(mod)
return NewMod
#############################################
# convert rigel module to magma & wire it to some magma stuff
RigelMod = rigelToMagma(p200)
print(RigelMod)
class Add210(m.Circuit):
IO = ["I",m.In(m.UInt(8)),"O",m.Out(m.UInt(8))]+m.ClockInterface()
@classmethod
def definition(io):
rm = RigelMod()
m.wire(io.I,rm.process_input)
out = rm.process_output+m.uint(10,8)
m.wire(io.O,out)
m.wire(rm.CE,m.bit(True))
m.compile("example",Add210)
